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W83793G winbond h/w monitor date: december 11, 2006 revision: 1.0
W83793G publication release date: dec. 11, 2006 - i - revision 1.0 W83793G data sheet revision history pages dates version web version main contents 1 n.a. 0.1 n.a. preliminary 2 n.a. 06/06/05 0.2 n.a. modify pi n type for vid pins. sec4.1 and 5.2 3 n.a. 08/01/05 0.3 add vtt and peci pin. 4 n.a. 0.32 n.a. 1. modify chap4(block diagram) and chap5(pin configuration) 5 n.a. 01/20/06 0.33 n.a. modify register for b version. 6 n.a. 01/06/06 0.34 n.a. 1. modify the formula to calculate the rpm 2. add information of ?the top marking? 3. change the part name to W83793G 7 page 9, 13, 14 02/27/06 0.35 n.a. add fanin9 ~fanin12 function description 8 12/1/06 1.0 1. modify 8.8.2.3 register description. 2. update 8.9.2.1 voltage reading formula 3. remove amd si description 4. update 8.3.2.2 i ndex 0ch i2caddr75b registers 5. update ac characteristic on chap 9.3
W83793G - ii - table of contents- 1. general des cription ......................................................................................................... 1 2. features ....................................................................................................................... .......... 2 2.1 monitoring items ............................................................................................................. 2 2.2 address resolution protocol and alert standar d format .............................................. 2 2.3 actions e nabling ............................................................................................................. 3 2.4 gener al ........................................................................................................................ ... 3 2.5 package ........................................................................................................................ .. 3 3. key specific ations ............................................................................................................. .3 4. block di agram .................................................................................................................. .... 4 5. pin config urati on .............................................................................................................. .5 6. pin descri ption................................................................................................................ ..... 6 6.1 pin type descr iption....................................................................................................... 6 6.2 pin descripti on list ......................................................................................................... 6 7. functional des cription ................................................................................................. 11 8. configuration registers .............................................................................................. 12 8.1 id, bank select regist ers............................................................................................. 12 8.1.1 id, bank select registers map...............................................................................12 8.1.2 id, bank select r egister de tails .............................................................................12 8.2 watch dog timer register s ......................................................................................... 14 8.2.1 watch dog timer r egisters map............................................................................14 8.2.2 watch dog timer r egister de tails .........................................................................15 8.3 configuration and address select regi sters................................................................ 17 8.3.1 register maps ........................................................................................................17 8.3.2 register details ......................................................................................................17 8.4 vid control/status regist ers........................................................................................ 20 8.4.1 vid control/status registers map..........................................................................20 8.4.2 vid register deta ils ...............................................................................................21 8.5 int/smi# control/st atus regi sters .............................................................................. 26 8.5.1 int/smi control/status register map ....................................................................27 8.5.2 int/smi control/status register details .................................................................27 8.6 ovt/beep control regist er......................................................................................... 33 8.6.1 ovt/beep control r egisters map .........................................................................33 8.6.2 ovt/beep control regi sters de tails .....................................................................33 8.7 multi-function pin c ontrol regi ster.............................................................................. 36 8.7.1 multi-function pin cont rol register map ................................................................36 8.7.2 multi-function pin contro l register details ............................................................37
W83793G publication release date: dec. 11, 2006 - iii - revision 1.0 8.8 temperature sensors control r egister ........................................................................ 40 8.8.1 temperature sensors cont rol register map ..........................................................40 8.8.2 temperature sensors cont rol register deta ils ...................................................... 40 8.9 voltage channel r egister s ........................................................................................... 44 8.9.1 voltage channel regi sters ma p .............................................................................44 8.9.2 voltage channel regi ster de tails ...........................................................................45 8.10 temperature channel regist ers .................................................................................. 48 8.10.1 temperature channel register map.......................................................................48 8.10.2 temperature channel r egister de tails ...................................................................49 8.11 fan control r egisters................................................................................................... 51 8.11.1 fan register map ...................................................................................................51 8.11.2 fan register deta ils ...............................................................................................56 8.12 peci control r egisters................................................................................................. 81 8.12.1 peci register map.................................................................................................82 8.12.2 peci register deta ils .............................................................................................83 8.13 asf control r egisters .................................................................................................. 89 8.13.1 asf register map ..................................................................................................89 8.13.2 asf register deta ils ..............................................................................................95 9. electrical chara cteristi cs....................................................................................... 112 9.1 absolute maxi mum rati ngs ........................................................................................ 112 9.2 dc characteri stics...................................................................................................... 112 9.3 ac characte ristic s ...................................................................................................... 114 9.3.1 access inte rface ...................................................................................................114 9.3.2 dynamic vcore li mit setti ng................................................................................. 115 9.3.3 power on reset ...................................................................................................116 10. order inform ation ......................................................................................................... 116 11. appendix ....................................................................................................................... ....... 117 11.1 register summary ...................................................................................................... 117 12. the top ma rking............................................................................................................... 1 25 13. package drawing a nd dimens ions ............................................................................ 126
W83793G publication release date: dec. 11, 2006 - 1 - revision 1.0 1. general description W83793G is an evolving version of the w83792d. be sides the conventional functions of w83792d, W83793G uniquely provides several innovative featur es such as asf 2.0 specification compliant, smbus 2.0 arp command compatible, 8 sets of smart fan tm . conventionally, W83793G can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system, such as server, workstation?etc, working very stably and efficiently. a 10-bit analog-to-digital converter (adc) is built inside W83793G. W83793G can simultaneously monitor 11 analog voltage inputs (including power vdd/5vsb/vbat monitoring), 12 fan tachometer inputs, 6 remote temperatures, 4 of which suppor t current mode (dual current source) temperature measurement method, and watch dog timer functi on. the sense of remote temperature can be performed by thermistors, or directly from intel? / amd tm cpu with thermal diode output. W83793G provides 8 pwm (pulse width modulation) / dc fan output modes for smart fan control - s thermal cruise tm t mode and s smart fan tm ii t mode. under s thermal cruise tm t mode, temperatures of cpu and the system can be maintained within s pecific programmable ranges under the hardware control. as smart fan tm ii, which provides 8 sets of temperatures point each could control fan?s duty cycle, depends on this construction, fan could be oper ated at the lowest possi ble speed so that the acoustic noise could be avoided. as for warning mechanism, W83793G provides smi#, ovt#, irq, beep signals for system protection ev ents. W83793G also has 2 specific pins to provide selectable address setting for application of multiple devices (up to 4 devices) wired through i 2 c interface. W83793G can uniquely serve as an asf sensor to respond to asf master?s request for the implementation of network managem ent in os-absent status. through W83793G?s compliance with asf2.0 sensor specification, network server is able to monitor the env ironmental status of each client in os-absent state by pet (platform event trap) frame values returned from W83793G, such as temperatures, voltages, fan speed and case open. moreover, W83793G supports smbus 2.0 arp command to solve the problem of address conflic ts by dynamically assigning a new unique address for W83793G asf function after W83793G?s udid is sent. through the application software or bios, the user s can read all the monitored parameters of the system from time to time. a pop-up warning can also be activated when the monitored item is out of the proper/preset range. the application software could be winbond's hardware doctor tm or other management application software. besides, the user s can set up the upper and lower limits (alarm thresholds) of these monitored parameters and activate corresponding maskable interrupts.
W83793G - 2 - 2. features 2.1 monitoring items voltage ? monitoring 11 voltages (3 power pins ? vsb, vcc, vbat, 8 external pins ? vcore x 4, +3v, +12v, others x 2). temperature ? 4 thermal diode (d+, d-) inputs, supporting cu rrent mode (dual current source) temperature measurement method ? 2 thermistor inputs ? support intel? peci fan ? 8 dc/pwm fan outputs for fan speed control ? 8 fan speed inputs for monitoring (up to 12 by register setups) ? smart fan tm -- control the most fitting speed aut omatically by temperature. caseopen ? case open detection input. 2.2 address resolution protocol and alert standard format ? support system management bus (smb us) version 2.0 specification ? comply with hardware sensor slav e arp (address resolution protocol) ? response asf 2.0 command --- get event da ta, get event status, device type poll ? comply with asf 2.0 sensors (monitoring fan s peed, voltage, temperature, thermal trip and case open event/status) ? support remote control subset: remote power-on/ power-off/ reset.
W83793G publication release date: dec. 11, 2006 - 3 - revision 1.0 2.3 actions enabling ? issue smi#, ovt# signals to activate system protection ? issue beep signal to activate system speaker or buzzer 2.4 general ? i p 2 p c serial bus interface ? watch dog timer function with pin: wdtrst#, sysrst_in. ? 2 pins (a0, a1) to provide selectable address setti ngs for application of multiple devices (up to 4 devices) wired together through i p 2 p c interface ? 5v operation 2.5 package ? 56 pin ssop 300mil. 3. key specifications voltage monitoring accuracy 1% z temperature sensor accuracy remote diode sensor accuracy 1 c resolution 0.5 supply voltage (pin 7, 5vsb) 5 0.25v z operating supply current 25 ma typ. current without 48mhz input at pin 1 8 ma typ. z adc resolution 10 bits
W83793G - 4 - 4. block diagram vid control control circuit & value ram current dispatcher amplify circuit channel mux 10-bits delta_sigma adc band gap reference watch dog time r beep/alert generator asf command decode r smbus & arp control smbus interface intel peci interface fan control vida 7:0 vidb 7:0 d+[1:4] d-[1:4] thr [1:2] vcore / v sen [1:2] vref sysrstin# wdtrst# caseo p en fanin [ 1:12 ] vtt peci scl sda addr [0:1] caseopen fanctrl [1:8] ovt#/beep pwrbtn# vidbsel irq/smi# W83793G
W83793G publication release date: dec. 11, 2006 - 5 - revision 1.0 5. pin configuration W83793G (56 ssop) clk ovt#/beep irq/smi# 1 2 3 4 5 6 scl sda pwrbtn# 7 8 9 10 5vsb caseopen# vbat vida4/fanin8 11 12 13 14 15 16 17 18 19 20 vida5/fanctl8 vida6 vida7 wdtrst# sysrstin# gnd peci vtt 21 22 23 24 25 26 27 28 vsen1 vsen2 vsen3 vsen4 vcorea vcoreb 5vdd vref thr1 thr2 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 vidb7/fanctl8 vidb6/fanin8 vidb5/fanctl7 vidb4/fanin7 vidb3/fanctl6 vidb2/fanin6 vidb1/fanctl5 vidb0/fanctl4 fanin5 fanin4 fanctl3/vidbsel fanin3 fanctl2/addr1 fanin2 fanctl1/addr0 fanin1 vida3/fanin12 vida2/fanin11 vida1/fanin10 vida0/fanin9 4_d- 4_d+ 3_d- 3_d+ 2_d- 2_d+ 1_d- 1_d+
W83793G - 6 - 6. pin description 6.1 pin type description symbol description t ttl level v1 vil/vih=0.4/0.6 level v2 vil/vih=0.8/1.4 level v3 vtt level s schmitt trigger 12 12ma sink/source capability out output pin od open-drain output pin aout output pin (analog) in input pin (digital) ain input pin(analog) 6.2 pin description list pin name pin no. power plane type description clk 1 5vsb in ts 48mhz system clock while vcc5v powered up. peci and fan will use this clock to drive logics. ovt# over temperature alert. low active. beep 2 5vsb od 12 beep output when abnormal event occurs. when this is no abnormal events, this pin asserts low. irq out 12 interrupt request output when abnormal events occur. smi# 3 5vsb od 12 system management interrupt (open drain). scl 4 5vsb in ts serial bus clock. sda 5 5vsb in/od 12ts serial bus bi-directional data. pwrbtn# 6 5vsb od 12 power button output for enable/disable power supply. this pin is related to asf commands. 5vsb 7 - power this pin is power for W83793G. bypass with the parallel combination of 10 f (electrolytic or tantalum) and 0.1 f (ceramic) bypass capacitors. caseopen# 8 vbat in ts case open detection. an active low input from an external device when case is intruded. this signal will be latched even the case is closed.
W83793G publication release date: dec. 11, 2006 - 7 - revision 1.0 pin description list, continued. pin name pin no. power plane type description vbat 9 power vbat supplies power for caseopen. besides, it is also a voltage monitor channel. vida4 in v1s or in v2s voltage supply readouts bit 4 from cpu a. (default) fanin8 10 5vsb in ts 0v to +5v amplitude fan tachometer input vida5 in v1s or in v2s voltage supply readouts bit 5 from cpu a. (default) fanctl8 out / od 12a fan control output. the 8 th fan control signal can be programmed to output through pin 56 or this pin. when this pin is programmed to be fan control signal, it only supports pwm mode. fanin12 11 5vsb in ts 0v to +5v amplitude fan tachometer input vida6 12 5vsb in v1s or in v2s voltage supply readouts bit 6 from cpu a. vida7 13 5vsb in v1s or in v2s voltage supply readouts bit 7 from cpu a. (default) wdtrst# 14 5vsb od 12 low active system reset. if triggered, this pin will send out 100ms low pulse for system reset. sysrstin# 15 5vsb in ts system reset input, used to control wdt. gnd 16 power system ground. peci 17 5vdd in/o v3 intel? cpu peci interface vtt 18 power intel? cpu vtt power vsen1 19 ain voltage sensor input. detect range is 0~4.096v vsen2 20 ain voltage sensor input. detect range is 0~4.096v +12vsen 21 - ain +12v voltage input for monitoring. this +12v input voltage needs external resistors to scale it down. the detect range is 0~2.048v. +3vsen 22 ain +3v voltage input for monitoring. the detect range is 0~4.096v.
W83793G - 8 - pin description list, continued. pin name pin no. power plane type description vcorea 23 ain cpu a core voltage input. detect range is 0~2.048v vcoreb 24 ain cpu b core voltage input. detect range is 0~2.048v. 5vdd 25 - power +5v vdd power. bypass with the parallel combination of 10 f (electrolytic or tantalum) and 0.1 f (ceramic) bypass capacitors. vref 26 aout reference voltage output. thr1 27 ain thermistor 1 terminal input. thr2 28 ain thermistor 2 terminal input. 1_d+ 29 ain thermal diode 1 d+ . 1_d- 30 ain thermal diode 1 d- . 2_d+ 31 ain thermal diode 2 d+ . 2_d- 32 ain thermal diode 2 d- . 3_d+ 33 ain thermal diode 3 d+ . 3_d- 34 ain thermal diode 3 d- . 4_d+ 35 ain thermal diode 4 d+ . 4_d- 36 ain thermal diode 4 d- . vida0 in v1s or in v2s voltage supply readouts bit 0 from cpu a. (default) fanin9 37 5vsb in ts 0v to +5v amplitude fan tachometer input vida1 in v1s or in v2s voltage supply readouts bit 1 from cpu a. (default) fanin10 38 5vsb in ts 0v to +5v amplitude fan tachometer input
W83793G publication release date: dec. 11, 2006 - 9 - revision 1.0 pin description list, continued. pin name pin no. power plane type description vida2 in v1s voltage supply readouts bit 2 from cpu a. (default) fanin11 39 5vsb in ts 0v to +5v amplitude fan tachometer input vida3 in v1s voltage supply readouts bit 3 from cpu a. (default) fanin12 40 5vsb in ts 0v to +5v amplitude fan tachometer input fanin1 41 5vsb in ts 0v to +5v amplitude fan tachometer input fanctl1 out / od 12 / aout fan speed control pwm/dc output. when the power of 5vdd is 0v, this pin will drive logic 0. the power of this pin is supplied by vsb 5v. as dc output, 64 steps output voltage scaled to 0~5vsb. addr0 42 5vsb in ts i 2 c device address bit 0 trapping during 5vsb power on. fanin2 43 5vsb in ts 0v to +5v amplitude fan tachometer input fanctl2 out / od 12 / aout fan speed control pwm/dc output. when the power of 5vdd is 0v, this pin will drive logic 0. the power of this pin is supplied by vsb 5v. as dc output, 64 steps output voltage scaled to 0~5vsb. addr1 44 5vsb in ts i 2 c device address bit 1 trapping during 5vsb power on. fanin3 45 5vsb in ts 0v to +5v amplitude fan tachometer input fanctl3 out / od 12 / aout fan speed control pwm/dc output. when the power of 5vdd is 0v, this pin will drive logic 0. the power of this pin is supplied by vsb 5v. as dc output, 64 steps output voltage scaled to 0~5vsb. vidbsel 46 5vsb in ts the pin straps fan mode and vid mode during 5vsb power on. . when the strap to high, it will select vid mode. when strapped to low, it will select fan mode for pin49~56.
W83793G - 10 - pin description list, continued. pin name pin no. power plane type description fanin4 47 5vsb in ts 0v to +5v amplitude fan tachometer input fanin5 48 5vsb in ts 0v to +5v amplitude fan tachometer input fanctl4 out / od 12 / aout fan speed control pwm/dc output. when the power of 5vdd is 0v, this pin will drive logic 0. the power of this pin is supplied by vsb 5v. as dc output, 64 steps output voltage scaled to 0~5vsb. vidb0 49 5vsb in v1s or in v2s voltage supply readouts bit 0 from cpu b. fanctl5 out / od 12 / aout fan speed control pwm/dc output. when the power of 5vdd is 0v, this pin will drive logic 0. the power of this pin is supplied by vsb 5v. as dc output, 64 steps output voltage scaled to 0~5vsb. vidb1 in v1s or in v2s voltage supply readouts bit 1 from cpu b. fanin9 50 5vsb ints 0v to +5v amplitude fan tachometer input fanin6 ints 0v to +5v amplitude fan tachometer input vidb2 51 5vsb in v1s or in v2s voltage supply readouts bit 2 from cpu b. fanctl6 out / od 12 / aout fan speed control pwm/dc output. when the power of 5vdd is 0v, this pin will drive logic 0. the power of this pin is supplied by vsb 5v. as dc output, 64 steps output voltage scaled to 0~5vsb. fanin10 ints 0v to +5v amplitude fan tachometer input vidb3 52 5vsb in v1s or in v2s voltage supply readouts bit 3 from cpu b. fanin7 ints 0v to +5v amplitude fan tachometer input vidb4 53 5vsb in v1s or in v2s voltage supply readouts bit 4 from cpu b.
W83793G publication release date: dec. 11, 2006 - 11 - revision 1.0 pin description list, continued. pin name pin no. power plane type description fanctl7 out / od 12 / aout fan speed control pwm/dc output. when the power of 5vdd is 0v, this pin will drive logic 0. the power of this pin is supplied by vsb 5v. as dc output, 64 steps output voltage scaled to 0~5vsb. fanin11 ints 0v to +5v amplitude fan tachometer input vidb5 54 5vsb in v1s or in v2s voltage supply readouts bit 5 from cpu b. fanin8 ints 0v to +5v amplitude fan tachometer input vidb6 55 5vsb in v1s or in v2s voltage supply readouts bit 6 from cpu b. fanctl8 out / od 12 / aout fan speed control pwm/dc output. the 8 th fan control signal can be programmed to output through pin 11 or this pin. when the power of 5vdd is 0v, this pin will drive logic 0. the power of this pin is supplied by vsb 5v. as dc output, 64 steps output voltage scaled to 0~5vsb. vidb7 56 5vsb in v1s or in v2s voltage supply readouts bit 7 from cpu b. 7. functional description this section is blank now. refer chap 8 for function description.
W83793G - 12 - 8. configuration registers 8.1 id, bank select registers W83793G inside resides three banks of registers, cust omer must set bank correctly so that correct registers can be accessed. all the register s described here can be access in all banks. 8.1.1 id, bank select registers map address 00 hex , 0d hex , 0e hex , 0f hex in all three register banks are reserved as id, bank select registers. mnemonic register name type banksel. bank select rw vendorid. winbond vendor id ro chipid. winbond chip id ro deviceid. winbond device version id ro 8.1.2 id, bank select register details 8.1.2.1 bank select register (bank select) three banks of registers are inside W83793G. the register bank could be selected by programming bank select register. all address 00 hex in these there banks is defined as bank select register. location: bank 0, 1, 2 address 00 hex type: read / write reset: vsb5v (pin 7) rising, init reset (cr40.bit7) is set, vdd5v (pin 25) rising @ rst_vdd_md (cr40.bit4) set, sysrstin_n (pin 15) falling @ sysrst_md (cr40.bit5) set. bankselect bit 7 6 5 4 3 2 1 0 name hbacs reserve bank select reset 1 0 hex 0 hex bit description 7 hbacs (high byte access) 0: return the low byte while reading winbond vendor id. 1: return the high byte while reading winbond vendor id. 6-3 reserved.
W83793G publication release date: dec. 11, 2006 - 13 - revision 1.0 continued bit description 2-0 bank select. 000 bin : bank 0 is selected to access. 001 bin : bank 1 is selected to access. 010 bin : bank 2 is selected to access. 8.1.2.2 winbond vendor id register (vender id) the winbond vendor id contains two by tes data. by programming register hbacs , it can customer can select to access either high or low byte of winbond vendor id. location: bank 0, 1, 2 address 0d hex type: read only reset: no reset vendorid (winbond vendor id) bit 7 6 5 4 3 2 1 0 name vendorid fixed 5c hex / a3 hex bit description 7-0 vendorid. return 5c hex if hbacs = 1; return a3 hex if hbacs = 0. 8.1.2.3 winbond chip id register (chipid) location: bank 0, 1, 2 address 0e hex type: read only reset: no reset chipid (winbond chip id) bit 7 6 5 4 3 2 1 0 name chipid reset 7b hex bit description 7-0 chipid. chip id of W83793G is 7b h ex
W83793G - 14 - 8.1.2.4 winbond version id register (device id) location: bank 0, 1, 2 address 0f hex type: read only reset: no reset version id bit 7 6 5 4 3 2 1 0 name deviceid fixed 11 hex /12 hex bit description 7-0 version id. device id of W83793G b version is 11 hex , c version is 12 hex 8.2 watch dog timer registers W83793G is built in with a watch dog timer, whic h enable users to reset the system by pin 14 while system becomes abnormal. once watch dog is enabled, W83793G starts to count down, and host should set the timer for further count down or clear /disable the timer to prevent W83793G issue reset signal. 8.2.1 watch dog timer registers map watch dog timer is consisted of four register s. wdtlock and enable_wdt are used to activate soft-wdt and hard-wdt, respectively. wdt_sts and downcounter can inform the host whether the system is time up or not. mnemonic register name type wdtlock. lock watch dog wo enablewdt. watch dog enable ro wdt_sts. watch dog status r/w downcounter. watch dog timer r/w two kinds of watchdog timer functions are support ed by W83793G. one is so-called soft watch dog timer, and the other is hard watch dog timer. hard watch dog timer if enabled that will start a 4 minutes wdt after completion of system reset. (a low to high transition on sysrstin# pin). bios need to write a 00 hex into watch dog timer register (04 hex ) to disable timer within 4 minutes, otherwise pin 14 wdtrst# will assert to reset system. soft watch dog timer will start down counting w henever timeout time is set and soft watch dog timer is enabled. a wdtrst# will be issued while the timer timeouts. soft watch dog timer will be disabled automatic ally after received a sysrstin_n low signal. bank0. cr40 [2]/ enwdt must set to 1 if there four watch dog timer registers want to be programming.
W83793G publication release date: dec. 11, 2006 - 15 - revision 1.0 8.2.2 watch dog timer register details 8.2.2.1 lock watch dog register (wdt lock) writing this register enable the soft watch dog timer or hard watch dog timer. this register is written only and user can confirm the write success by reading enable_wdt. location: bank 0 address 01 hex type: write only reset: vsb5v (pin 7) rising, sysrstin_n (pin 15) falling in soft wdt mode. wdtlock (watch dog timer lock) bit 7 6 5 4 3 2 1 0 name unlock code bit description 7-0 unlock code. write 55 hex , enable soft watch dog timer. write aa hex , disable soft watch dog timer. write 33 hex , enable hard watch dog timer. write cc hex , disable hard watch dog timer. 8.2.2.2 watch dog enable register (enable wdt) location: bank 0 address 02 hex type: read only reset: vsb5v (pin 7) rising. enable wdt (watch dog timer enable status) bit 7 6 5 4 3 2 1 0 name reserve hard soft reset 0 0 0 0 0 0 0 0
W83793G - 16 - bit description 7-2 reserved 1 hard. 1: indicates the hard watch dog is enabled. 0: hard watch dog is disabled. 0 soft. 1: indicates the soft watch dog is enabled. 0: soft watch dog is disabled. 8.2.2.3 watch dog status register location: bank 0 address 03 hex type: read / write reset: vsb5v (pin 7) rising. wdt_sts (watch dog status) bit 7 6 5 4 3 2 1 0 name reserve reserve reserve reserve wdt stage hard_to soft_to reset 0 0 0 0 0 0 0 0 bit description 7-4 reserved 3-2 wdt stage. these 2 bits record last wdt stage for bios readout. the information is used to help bios to identify wdt timeout issue. 1 hard_to. 1: a hard timeout occurs. this bit will be cleared after reading. 0 soft_to. 1: a soft timeout occurs. this bit will be cleared after reading. 8.2.2.4 watch dog timer register (down counter) location: bank 0 address 04 hex type: read / write reset: vsb5v (pin 7) rising.
W83793G publication release date: dec. 11, 2006 - 17 - revision 1.0 down counter (watch dog timer) bit 7 6 5 4 3 2 1 0 name timeout time reset 00 hex bit description 7-0 timeout time. to write 00 hex can disable timer while in hard watch dog timer mode. to set timeout time for soft watch dog timer, unit is min. the timeout time is unit in minutes, and 0 represent s the timer is timeout or cleared. 1 represents there still have 1 sec to 1 minute for this timer. in th is fashion, 2 shows time to time up is 1 minute 1 sec to 2 minutes. 8.3 configuration and address select registers 8.3.1 register maps 8.3.1.1 i 2 c address registers map mnemonic register name type i2caddr i 2 c address r/w tempd1/2addr lm75 temperature sensor i 2 c address r/w there are four addresses (58 hex , 5a hex , 5c hex , 5e hex ) can be assigned for W83793G i 2 c interface. and it also provides four i 2 c addresses for each lm75-like temperature sensor (90 hex , 92 hex , 94 hex , 96 hex for td1 and 98 hex , 9a hex , 9c hex , 9e hex for td2). these three addresses can be set by trapping pin 42 & 44 input value at 100ms after power ready. the registers for temperature sensor d1 & d2 can also be accessed by respective addresses that set as i 2 c address of W83793G. the lm75-like functions default are enabled and can be disabled by setting bit 3 and bit 7 of tempd1/2addr to 1. 8.3.1.2 configuration register maps mnemonic register name type config configuration register r/w configuration register controls the system reset source, stop, power down and warning output mode. 8.3.2 register details 8.3.2.1 i 2 c address register (i2caddr) location: bank 0 address 0b hex type: read / write reset: 100ms after vsb5v (pin 7) rising.
W83793G - 18 - i2caddr bit 7 6 5 4 3 2 1 0 name smbusaddr bit description 7-0 smbusaddr. the value of smbusaddr is trapping pin voltage on paddr0 (pin42) and paddr1 (pin44) at 100ms after vsb power ready. addr1 addr0 i 2 c address 0 0 58 hex 0 1 5a hex 1 0 5c hex 1 1 5e hex 8.3.2.2 lm75-like temperature sensor i 2 c address register location: bank 0 address 0c hex type: read / write reset: 100ms after vsb5v (pin 7) rising. tempd1/2addr bit 7 6 5 4 3 2 1 0 name dis_td2 i2caddr75b dis_td1 i2caddr75a reset 0 trapped value 0 trapped value bit description 7 dis_td2. if set to 1, it cannot access registers for te mperature sensor 2 by temperature sensor 2 i2c address. 6-4 i2caddr75b. the value of i2caddr75b is trapping paddr0 (pin42) and paddr1 (pin44) at 100ms after vsb power good issue. addr1 addr0 i2caddr75b temperature sensor 2 i2c address 0 0 100 98 hex 0 1 101 9a hex 1 0 110 9c hex 1 1 111 9e hex 3 dis_td1. if set to 1, it cannot access registers for te mperature sensor 1 by temperature sensor 1 i2c address.
W83793G publication release date: dec. 11, 2006 - 19 - revision 1.0 continued. bit description 2-0 i2caddr75a. the value of i2caddr75b is trapping paddr0 (pin42) and paddr1 (pin44) at 100ms after vsb power good issue. addr1 addr0 i2caddr75a temperature sensor 1 i2c address 0 0 000 90 hex 0 1 001 92 hex 1 0 010 94 hex 1 1 011 96 hex 8.3.2.3 configuration register location: bank 0 address 40 hex type: read / write reset: bit 0~3 & 7: vsb5v (pin 7) rising, init reset (cr40.bit7) is set, vdd5v (pin 25) rising @ rst_vdd_md (cr40.bit4) set, sysrstin_n (pin 15) falling @ sysrst_md (cr40.bit5) set. bit 4 & 5: vsb5v (pin 7) rising, init reset (cr40.bit7) is set. config bit 7 6 5 4 3 2 1 0 name init reserve sysrst_md rst_vdd_md en_bat_mnt en_wdt int_clear start reset 0 0 0 0 0 0 0 0 bit description 7 init. set one restores power on default value to a ll registers except the serial bus address register. this bit clears itself since the power on default is zero. 6 reserved 5 sysrst_md. write 1, whole chip will reset when sysrstin# input. write 0, no any operation when sysrstin# input. 4 rst_vdd_md. write 1, whole chip will reset when 5v dd up. write 0, no any operation when 5vdd up.
W83793G - 20 - continued bit description 3 en_bat_mnt. write 1, enable battery voltage monitor. write 0, disable battery voltage monitor. if enable this bit, the monitor value is valid after one monitor cycle. 2 en_wdt. set this bit to 1 will enable the watch d og timer function. watch dog timer function will reset system (pin 47) while it timeouts. 1 int_clear. a one disables the smi# and irq# outputs wi thout affecting the contents of interrupt status registers. the device will stop monito ring at last channel. it will resume upon clearing of this bit. 0 start. 1 : enables startup of monitoring operations; 0 : puts the analog part in power-down mode. 8.4 vid control/status registers W83793G provides dual vcore monitoring channels. vcore channels are automatically monitored once 5vsb applied onto W83793G, but W83793G will issue alert information only when their corresponding high/low limit is being violated. asf is also based on these limit register to judge the current channel status and report to host. two methods are used to assign the vcore limits. a ssigning it manually; or a ssigning it automatically by vid inputs. the following registers set c an let users choose their preferred method. 8.4.1 vid control/status registers map mnemonic register name type vidin_a vida input value ro vidin_b vidb input value ro vida_latch vida latch value ro vidb_latch vidb latch value ro vid_control vid control r/w vcore_limhi vcore high tolerance r/w vcore_limlo vcore low tolerance r/w W83793G supplies two sets of vid input pin for vocrea and vcoreb channels. if dynamic vid function is enabled, the high/low limit of vc orea and vcoreb channel will auto-update while vid input value change. some vida and all vidb input pins are multi function pin. it needs programming bank0 cr58 multi function pin control registers adequately.
W83793G publication release date: dec. 11, 2006 - 21 - revision 1.0 8.4.2 vid register details 8.4.2.1 vida input value register (vidin_a) location: bank 0 address 05 hex type: read only vidin_a bit 7 6 5 4 3 2 1 0 name vidain7 vidain6 vidain5 vidain4 vidain3 vidain2 vidain1 vidain0 bit description 1 int_clear. a one disables the smi# and irq# outputs wi thout affecting the contents of interrupt status registers. the device will stop monito ring at last channel. it will resume upon clearing of this bit. 7 vidain7. real time pin 13 input value. that is available for vrm11 only. 6 vidain6. real time pin 12 input value. that is available for vrm10 and vrm11 only. 5 vidain5. real time pin 11 input value. that is available for vrm10, vrm11 and amd opterontm 6- bit vid only. 4 vidain4. real time pin 10 input value. 3 vidain3. real time pin 40 input value. 2 vidain2. real time pin 39 input value. 1 vidain1. real time pin 38 input value. 0 vidain0. real time pin 37 input value.
W83793G - 22 - 8.4.2.2 vidb input value register (vidin_b) location: bank 0 address 06 hex type: read only vidin_b bit 7 6 5 4 3 2 1 0 name vidbin7 vidbin6 vidbin5 vidbin4 vidbin3 vidbin2 vidbin1 vidbin0 bit description 7 vidbin7. real time pin 56 input value. that is available for vrm11 only. 6 vidbin6. real time pin 55 input value. that is available for vrm10 and vrm11 only. 5 vidbin5. real time pin 54 input value. that is available for vrm10, vrm11 and amd opteron tm 6-bit vid only. 4 vidbin4. real time pin 53 input value. 3 vidbin3. real time pin 52 input value. 2 vidbin2. real time pin 51 input value. 1 vidbin1. real time pin 50 input value. 0 vidbin0. real time pin 49 input value. 8.4.2.3 vida latch value register (vida_latch) previous vidin_a and vidin_b allows user to readout the current value on vid pins, but vida_latch and vidb_latch can let users to keep the vi d value at any time by assigning the latch_vida / latch_vidb bits to 1. location: bank 0 address 07 hex type: read only vida_latch bit 7 6 5 4 3 2 1 0 name vida7 vida6 vida5 vida4 vida3 vida2 vida1 vida0
W83793G publication release date: dec. 11, 2006 - 23 - revision 1.0 bit description 7 vida7. to read this bit will return vida7 register value if latch_vida is set to 1 else return the pin value of vidain7. 6 vida6. to read this bit will return vida6 register value if latch_vida is set to 1 else return the pin value of vidain6. 5 vida5. to read this bit will return vida5 register value if latch_vida is set to 1 else return the pin value of vidain5. 4 vida4. to read this bit will return vida4 register value if latch_vida is set to 1 else return the pin value of vidain4. 3 vida3. to read this bit will return vida3 register value if latch_vida is set to 1 else return the pin value of vidain3. 2 vida2. to read this bit will return vida2 register value if latch_vida is set to 1 else return the pin value of vidain2. 1 vida1. to read this bit will return vida1 register value if latch_vida is set to 1 else return the pin value of vidain1. 0 vida0. to read this bit will return vida0 register value if latch_vida is set to 1 else return the pin value of vidain0. 8.4.2.4 vidb latch value register (vidb_latch) location: bank 0 address 08 hex type: read only vidb_latch bit 7 6 5 4 3 2 1 0 name vidb7 vidb6 vidb5 vidb4 vidb3 vidb2 vidb1 vidb0
W83793G - 24 - bit description 7 vidb7. to read this bit will return vidb7 register value if latch_vidb is set to 1 else return the pin value of vidbin7. 6 vidb6. to read this bit will return vidb6 register value if latch_vidb is set to 1 else return the pin value of vidbin6. 5 vidb5. to read this bit will return vidb5 register value if latch_vidb is set to 1 else return the pin value of vidbin5. 4 vidb4. to read this bit will return vidb4 register value if latch_vidb is set to 1 else return the pin value of vidbin4. 3 vidb3. to read this bit will return vidb3 register value if latch_vidb is set to 1 else return the pin value of vidbin3. 2 vidb2. to read this bit will return vidb2 register value if latch_vidb is set to 1 else return the pin value of vidbin2. 1 vidb1. to read this bit will return vidb1 register value if latch_vidb is set to 1 else return the pin value of vidbin1. 0 vidb0. to read this bit will return vidb0 register value if latch_vidb is set to 1 else return the pin value of vidbin0. 8.4.2.5 vid control register (vid_control) location: bank 0 address 59 hex type: read / write reset: vsb5v (pin 7) rising, init reset (cr40.bit7) is set, vdd5v (pin 25) rising @ rst_vdd_md (cr40.bit4) set, sysrstin_n (pin 15) falling @ sysrst_md (cr40.bit5) set. vid_control bit 7 6 5 4 3 2 1 0 name level_select en_dvid latch_vidb latch_vida vid_sel reset 00 bin 0 0 0 001 bin
W83793G publication release date: dec. 11, 2006 - 25 - revision 1.0 bit description 7-6 level_select. set vid input pin v ih /v il level 00 bin : 0.6v/0.4 for vrm10, 11 01 bin : 1.6v/0.8v for amd vid 10 bin : 2.0v/0.8v 11 bin :.reserved. 5 en_dvid. write 1, dynamic vid function is enabled. if vid changed, auto-updating high/low limit of corresponding vcore sensing voltage. if programming high/low limit of vcore sensing voltage manually is required, this bit has to be cleared as 0. 4 latch_vidb. write 1, cr08 latches current pin value of vidb. 3 latch_vida. write 1, cr07 latches current pin value of vida. 2-0 vid_sel. selectable vid tables: 000 bin : reserved 001 bin : vrm10 (default) 010 bin : vrm11 011 bin : amd opteron tm 5 bit vid codes 100 bin : amd opteron tm 6 bit vid codes 8.4.2.6 vcore high tolerance register (vcore_limhi) location : bank 0 address 09 hex type : read / write reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set.
W83793G - 26 - vcore_limhi bit 7 6 5 4 3 2 1 0 name vcore high tolerance reset 64 hex bit description 7-0 vcore high tolerance. while enable dynamic vid function (set bank0 cr59 bit5 to 1), writing tolerance register will force vcore limit updated with new voltage limit for vcore. the unit is 2mv 8.4.2.7 vcore low tolerance register (vcore_limlo) location : bank 0 address 0a hex type : read / write reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set. vcore_limlo bit 7 6 5 4 3 2 1 0 name vcore low tolerance reset 64 hex bit description 7-0 vcore low tolerance. while enable dynamic vid function (set bank0 cr59 bit5 to 1), writing tolerance register will force vcore limit generator gener ate new voltage limit for vcore. the unit is 2mv 8.5 int/smi# control/status registers several mechanisms are provided to alarm system when monitored channels are abnormal. at this paragraph, three kinds of control/st atus registers are introduced, ?real time status?, shows currently status of each channel; ?channel mask?, defines which channel need issue warning when abnormal, and when channel should not be cared due to floating or other circumstances. final one, ?interrupt status?, it gives host information of which channel is issuing alert, and host can base on this channel and do proper process to ensure system reliable.
W83793G publication release date: dec. 11, 2006 - 27 - revision 1.0 8.5.1 int/smi control/status register map mnemonic register name type int_sts1 int_sts5 interrupt status 1 interrupt status 5 ro mask1 mask5 smi/irq mask 1 smi/irq mask 5 r/w real_sts1 real_sts5 real time status 1 real time status 5 ro smiint_ctrl smi/irq control r/w pin 3 of W83793G is a multi-function pin. it can be the irq output or the smi# output signal. the function is selected by programming bank0 cr50 smi/irq control register. the interrupt mode for voltage and fanin is only two-time interrupt mode. for temperature, there are three modes to serv e: <1> comparator mode, <2>one-time interrupt mode, and <3> two-time interrupt mode. 8.5.2 int/smi control/status register details 8.5.2.1 interrupt status register (int_sts) a one represents corresponding channel have been exceed its limit. read interrupt status will clear the interrupt flag. vidchg will assert while vid are on the fly. it indicates vid have change in last 1ms. tart will assert while target temperature cannot be achieved after 3 minutes full speed of corresponding fan. location: int_sts1 - bank 0 address 41 hex int_sts2 - bank 0 address 42 hex int_sts3 - bank 0 address 43 hex int_sts4 - bank 0 address 44 hex int_sts5 - bank 0 address 45 hex type: read only reset: vsb5v (pin 7) rising, init reset (cr40.bit7) is set, vdd5v (pin 25) rising @ rst_vdd_md (cr40.bit4) set, sysrstin_n (pin 15) falling @ sysrst_md (cr40.bit5) set.
W83793G - 28 - int_sts1 bit 7 6 5 4 3 2 1 0 name 12vsen 3vsen vsen2 vsen1 reserve vtt vcoreb vcorea reset 0 0 0 0 0 0 0 0 int_sts2 bit 7 6 5 4 3 2 1 0 name td4 td3 td2 td1 vidchg vbat 5vsb 5vdd reset 0 0 0 0 0 0 0 0 int_sts3 bit 7 6 5 4 3 2 1 0 name fanin6 fanin5 fanin4 fanin3 fanin2 fanin1 tr2 tr1 reset 0 0 0 0 0 0 0 0 int_sts4 bit 7 6 5 4 3 2 1 0 name reserve chassis fanin12 fanin11 fanin10 fanin9 fanin8 fanin7 reset 0 0 0 0 0 0 0 0 int_sts5 bit 7 6 5 4 3 2 1 0 name reserve tart6 tart5 tart4 tart3 tart2 tart1 reset 0 0 0 0 0 0 0 0 8.5.2.2 smi/irm mask register (mask) set to one will disable the corresponding interrupt s ources. clear to 0 will enable that interrupt source. smi mask4 bit 7 is clr_chs (clear chassis), writ e this bit with an one will clear internal caseopen latch, and after latch is clear, clr_chs will be reset to 0 itself. location: mask1 - bank 0 address 46 hex mask2 - bank 0 address 47 hex mask3 - bank 0 address 48 hex mask4 - bank 0 address 49 hex mask5 - bank 0 address 4a hex
W83793G publication release date: dec. 11, 2006 - 29 - revision 1.0 type: read / write reset: vsb5v (pin 7) rising, init reset (cr40.bit7) is set, vdd5v (pin 25) rising @ rst_vdd_md (cr40.bit4) set, sysrstin_n (pin 15) falling @ sysrst_md (cr40.bit5) set. mask1 bit 7 6 5 4 3 2 1 0 name 12vsen 3vsen vsen2 vsen1 reserve vtt vcoreb vcorea reset 0 0 0 0 0 0 0 0 mask2 bit 7 6 5 4 3 2 1 0 name td4 td3 td2 td1 vidchg vbat 5vsb 5vdd reset 0 0 0 0 0 0 0 0 mask3 bit 7 6 5 4 3 2 1 0 name fanin6 fanin5 fanin4 fanin3 fanin2 fanin1 tr2 tr1 reset 0 0 0 0 0 0 0 0 mask4 bit 7 6 5 4 3 2 1 0 name clr_chs chassis fanin12 fanin11 fanin10 fanin9 fanin8 fanin7 reset 0 0 0 0 0 0 0 0 mask5 bit 7 6 5 4 3 2 1 0 name reserve tart6 tart5 tart4 tart3 tart2 tart1 reset 0 0 0 0 0 0 0 0
W83793G - 30 - 8.5.2.3 real time status register (real_sts) real-time status registers show the related channel exceeding limit or not at the polling moment. return 1 represents related channel has exc eeded the limit defined in limit registers. location : real_sts1 - bank 0 address 4b hex real_sts2 - bank 0 address 4c hex real_sts3 - bank 0 address 4d hex real_sts4 - bank 0 address 4e hex real_sts5 - bank 0 address 4f hex type : read only reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set. real_sts1 bit 7 6 5 4 3 2 1 0 name 12vsen 3vsen vsen2 vsen1 reserve vtt vcoreb vcorea reset 0 0 0 0 0 0 0 0 real_sts2 bit 7 6 5 4 3 2 1 0 name td4 td3 td2 td1 vidchg vbat 5vsb 5vdd reset 0 0 0 0 0 0 0 0 real_sts3 bit 7 6 5 4 3 2 1 0 name fanin6 fanin5 fanin4 fanin3 fanin2 fanin1 tr2 tr1 reset 0 0 0 0 0 0 0 0 real_sts4 bit 7 6 5 4 3 2 1 0 name reserve chassis fanin12 fanin11 fanin10 fanin9 fanin8 fanin7 reset 0 0 0 0 0 0 0 0
W83793G publication release date: dec. 11, 2006 - 31 - revision 1.0 real_sts5 bit 7 6 5 4 3 2 1 0 name reserve tart6 tart5 tart4 tart3 tart2 tart1 reset 0 0 0 0 0 0 0 0 8.5.2.4 smi/irq control register (smiint_ctrl) location : bank 0 address 50 hex type : read / write reset : vsb5v(pin 7) rising, init reset (cr40.bit7) is set, vdd5v (pin 25) rising @ rst_vdd_md (cr40.bit4) set, sysrstin_n (pin 15) falling @ sysrst_md (cr40.bit5) set. smiint_ctrl bit 7 6 5 4 3 2 1 0 name reserve irq_md irqsel temp_smi_md en_irqsmi pol reset 0 0 0 0 0 0 0 0 bit description 7-6 reserved. 5 irq_md. set 0, irq output level signal. set 1, output 200 us pulse signal. default is 0. 4 irq_sel. set pin 3 to irq mode. while 1 and en_irqsmi set to 1, pin 3 enabled with irq interrupt output. 3-2 temp_smi_md. temperature smi# mode select. 00 bin : comparator interrupt mode:(default) temperature td1/td2/ td3/td4/tr1/tr2 exceeds t o (over-temperature) limit causes an interrupt and this interrupt will be rese t by reading all the interrupt status. 01 bin : two time interrupt mode: these bits use in temperature sensor td1/td2/td3/td4/tr1/tr2 interrupt mode with hysteresis type. temperature exceeding t o (critical temperature), causes an interrupt and then temperature going below t hyst (critical temperature hysteresis) will also cause an interrupt if the previous interrupt has been rese t by reading all the interrupt status register. once an interrupt event has occurred by exceeding t o (critical temperature), then reset, if the temperature remains above the t hyst (critical temperature hysteresis).
W83793G - 32 - continued bit description 3-2 10 bin : one time interrupt mode: this bit use in temperature sensor td1/td2/td3/td4/tr1/tr2 interrupt mode with hysteresis type. temperature exceeding t o (critical temperature) causes an interrupt and then temperature going below t hyst (critical temperature hysteresis) will not cause an interrupt. once an interrupt event has occurred by exceeding t o (critical temperature), then going below t hyst (critical temperature hysteresis), and interrupt will not occur again until the temperature exceeding t o (critical temperature). 11 bin : two time non-related interrupt mode: this bit use in temperature sensor td1/td2/td3/td4/tr1/tr2 interrupt mode with hysteresis type. temperature exceeding t o , causes an interrupt and then temperature going below t hyst will also cause an interrupt. once an interrupt event has occurred by exceeding t o , then reset, if the temperature remains above the t hyst . if this mode is selected, for all monitor c hannels (it is not necessary to read the status for generating the next irq/smi# pulse. t critical t warning smi# ** ** ** twarning -hysteresis tcrit -hysteresis ** two-time intrrupt mode ** : interrupt status is read note: it can be programmed to be as not necessary to read the status for generating the next smi# pulse by setting temp_smi_md = 2'b11. 1 en_irqsmi. a one enables the irq/smi# interrupt output. 0 pol . (polarity) when set to 1, irq/smi# active hi gh. set to 0, irq/smi# active low.
W83793G publication release date: dec. 11, 2006 - 33 - revision 1.0 8.6 ovt/beep control register another solution to deal with abnormal situation is through ovt(over temperature) or beep. ovt, as it naming, represents for temperature abnormal is happening. in some applications, it can be combined with fan control and used to throttle the fan speed. beep can directly use sound of two tones to info rm user system abnormal. unlike ovt, beep can associate with any channel. 8.6.1 ovt/beep control registers map mnemonic register name type ovt_ctrl ovt control r/w ovt_beepen ovt/beep global enable r/w beep_ctrl1 beep_ctrl5 beep control 1 beep control 5 r/w pin 2 of W83793G is also a multi-function pin. it can be ovt# output signal or beep output signal and be selected by programming bank0 cr52 ovt/beep control register. 8.6.2 ovt/beep control registers details 8.6.2.1 ovt control register (ovt_ctrl) location : bank 0 address 51 hex type : read / write reset : vsb5v(pin 7) rising. ovt_ctrl bit 7 6 5 4 3 2 1 0 name ovt_md en_ovtr2 en_ovtr1 en_ovtd4 en_ovtd3 en_ovtd2 en_ovtd1 ovtpol reset 0 0 0 0 0 0 0 0
W83793G - 34 - bit description 7 ovt_md. there are two ovt# signal output type. 0 bin : comparator mode: (default) temperature exceeding tcritical (criti cal temperature) causes the ovt# output activated until the temperature is less than t hyst (critical temperature hysteresis). 1 bin : interrupt mode: setting temperature exceeding tcritical (c ritical temperature) causes the ovt# output activated indefinitely until reset reading tem perature sensor td1/ td2/td3/td4/tr1/tr2 registers. temperature exceeding tcritical (critical temperature), then ovt# reset, and then temperature going below t hyst (critical temperature hysteres is) will also cause the ovt# activated indefinitely until reset by reading temperature sensor td1/td2/td3/td4/tr1/tr2(reading interrupt status). once t he ovt# will not be activated by exceeding tcritical (critical temperature), then reset, if the temperature remains above t hyst (critical temperature hysteresis), the ovt# will not be activated again. 6 en_ovtr2. enable temperature sensor tr2 over-temper ature (ovt) output if set to 1. default 0; disable ovtr2 output through pin ovt#. the pin ovt# is wire or with ovtd1, ovtd2, ovtd3, ovtd4 and ovtr1. 5 en_ovtr1. enable temperature sensor tr1 over-temper ature (ovt) output if set to 1. default 0; disable ovtr1 output through pin ovt#. the pin ovt# is wire or with ovtd1, ovtd2, ovtd3, ovtd4 and ovtr2. 4 en_ovtd4. enable temperature sensor td4 over-temper ature (ovt) output if set to 1. default 0; disable ovtd4 output through pin ovt#. the pin ovt# is wire or with ovtd1, ovtd2, ovtd3, ovtr1 and ovtr2 3 en_ovtd3. enable temperature sensor td3 over-temper ature (ovt) output if set to 1. default 0; disable ovtd3 output through pin ovt#. the pin ovt# is wire or with ovtd1, ovtd2, ovtd4, ovtr1 and ovtr2 2 en_ovtd2. enable temperature sensor td2 over-temper ature (ovt) output if set to 1. default 0; disable ovtd2 output through pin ovt#. the pin ovt# is wire or with ovtd1, ovtd3, ovtd4, ovtr1 and ovtr2 1 en_ovtd1. enable temperature sensor td1 over-temper ature (ovt) output if set to 1. default 0; disable ovtd1 output through pin ovt#. the pin ovt# is wire or with ovtd2, ovtd3, ovtd4, ovtr1 and ovtr2 0 ovtpol. write 1, ovt# active high. write 0, ovt# active low.
W83793G publication release date: dec. 11, 2006 - 35 - revision 1.0 8.6.2.2 ovt/beep global enable register (ovt_beepen) location : bank 0 address 52 hex type : read / write reset : vsb5v(pin 7) rising. ovt_beepen bit 7 6 5 4 3 2 1 0 name reserved beepsel en_beep en_ovt reset 0 0 0 0 0 0 0 0 bit description 7-3 reserved. 2 beepsel. 1 : direct beep signal to pin 2. 0 : direct ovt signal to pin 2. 1 en_beep. (beep output global enable) 1 : beep is enabled, customer can sele ct event trigger source from beep_ctrl. 0 : beep is disabled. 0 enovt. (ovt output global enable) 1 : ovt is enabled, users can select ovt trigger source from ovt_ctrl. 0 : ovt is disable. 8.6.2.3 beep control register (beep_ctrl) set to one will enable the corresponding beep output. clear to 0 will disable that beep output. location: beep_ctrl1 - bank 0 address 53 hex beep_ctrl2 - bank 0 address 54 hex beep_ctrl3 - bank 0 address 55 hex beep_ctrl4 - bank 0 address 56 hex beep_ctrl5 - bank 0 address 57 hex type: read / write reset: vsb5v (pin 7) rising, init reset (cr40.bit7) is set, vdd5v (pin 25) rising @ rst_vdd_md (cr40.bit4) set, sysrstin_n (pin 15) falling @ sysrst_md(cr40.bit5) set.
W83793G - 36 - beep_ctrl1 bit 7 6 5 4 3 2 1 0 name 12vsen 3vsen vsen2 vsen1 reserve vtt vcoreb vcorea reset 0 0 0 0 0 0 0 0 beep_ctrl2 bit 7 6 5 4 3 2 1 0 name td4 td3 td2 td1 reserve vbat 5vsb 5vdd reset 0 0 0 0 0 0 0 0 beep_ctrl3 bit 7 6 5 4 3 2 1 0 name fanin6 fanin5 fanin4 fanin3 fanin2 fanin1 tr2 tr1 reset 0 0 0 0 0 0 0 0 beep_ctrl4 bit 7 6 5 4 3 2 1 0 name reserve chassis fanin12 fanin11 fanin10 fanin9 fanin8 fanin7 reset 0 0 0 0 0 0 0 0 beep_ctrl5 bit 7 6 5 4 3 2 1 0 name reserve tart6 tart5 tart4 tart3 tart2 tart1 reset 0 0 0 0 0 0 0 0 8.7 multi-function pin control register many functions exhibited in W83793G are not default function, and they might share pin out with other functions. here lists three registers defines the function enable registers. 8.7.1 multi-function pin control register map mnemonic register name type mfc multi-function pin control r/w fanin_ctrl fanin control r/w fan_sel fanin input pin redirection r/w in W83793G pin 10~13, pin 37~40, pin 49~56 are mu lti-function pin. all non-default functions are enabled by setting bank0 cr58, cr5c and cr5d.
W83793G publication release date: dec. 11, 2006 - 37 - revision 1.0 8.7.2 multi-function pin control register details 8.7.2.1 multi-function pin control register (mfc) location: bank 0 address 58 hex type: read / write reset: bit 0~6: vsb5v (pin 7) rising, init reset (cr40.bit7) is set, vdd5v (pin 25) rising @ rst_vdd_md (cr40.bit4) set, sysrstin_n (pin 15) falling @ sysrst_md (cr40.bit5) set. bit7: trapping at 100ms after vsb5v (pin 7) rising. mfc bit 7 6 5 4 3 2 1 0 name vidbsel sib_sel sid_sel sic_sel sia_sel fan8sel reset trap 0 0 0 0 0 0 0 bit description 7 vidbsel. pin 49~56 function select. power on trapping input value of pin 46. 1 bin : pin49~56 are vidb. 0 bin : pin 49~54 are fan speed control output or fan tachometer input; function of pin 55~56 is controlled by bit sib_sel. 6 sib_sel. while vidbsel is 0, si b_sel set function of pin55~56: 0 bin: pin55~56 are fanin8/fanctrl8. 1 bin : reserved. this bit must be set to 0. 5-4 sid_sel. set function of pin39~40: 0x bin : pin 39~40 are vida2/vida3. 10 bin : pin 39~40 are fanin1/fanin12. 11 bin :reserved. these two bits should not be set to 11 bin .
W83793G - 38 - continued. bit description 3-2 sic_sel. set function of pin37~38: 0x bin : pin 37~38 are vida0/vida1. 10 bin : pin 37~38 are fain9/fani10. 11 bin :. reserved. these two bits should not be set to 11 bin . 1 sia_sel. set function of pin12~13: 0 bin : pin 12~13 are vida6/vida7. 1 bin :. reserved. this bit must be set to 0. 0 fan8sel. set function of pin10~11: 0 bin : pin 10~11 are vida4/vida5. 1 bin : pin 12~13 are fanin8/fanctrl8. 8.7.2.2 fanin control register (fanin_ctrl) the register enables setup the functions of mult i-function fan inputs, while reset it is cleared. (00 hex ) location: bank 0 address 5c hex type: read / write reset: vsb5v (pin 7) rising, init reset (cr40.bit7) is set, vdd5v (pin 25) rising @ rst_vdd_md (cr40.bit4) set, sysrstin_n (pin 15) falling @ sysrst_md (cr40.bit5) set. fanin_ctrl bit 7 6 5 4 3 2 1 0 name reserve en_fanin12 en_fanin11 en_fanin10 en_fanin9 en_fanin8 en_fanin7 en_fanin6 reset 0 0 0 0 0 0 0 0 bit description 7 reserved. 6 en_fanin12 .(fan in 12 enable bit) 1 : if sid_sel = 10 bin , enable fanin12 monitor. 0 : disable . default is vid function.
W83793G publication release date: dec. 11, 2006 - 39 - revision 1.0 continued. bit description 5 en_fanin11 .(fan in 11 enable bit) if sid_sel = 10, setting to 1 will enable fanin11 monitor. if cleared, pin39 can be selected as processor a vid bit 2(en_d-vid). 4 en_fanin10 .(fan in 10 enable bit) if sic_sel = 10, setting to 1 will enable fanin10 monitor. if cleared, pin 38 can be selected as processor a vid bit 1. 3 en_fanin9 .(fan in 9 enable bit) if sic_sel = 10, setting to 1 will enable fanin9 monitor. if cleared, pin 37 can be selected as processor a vid bit 0(en_d-vid). 2 en_fanin8 .(fan in 8 enable bit) setting to 1 enables fanin8 monitor. if fanin8 connect to pin55 is desired, setting vidbsel = 0, sidb_sel = 0 and fan8sel = 0 are must. if fanin8 connect to pin 10, setting fan8sel = 1 is a must. setting to 0 enables pin 10 with processor a vid bit 4(en_d-vid) 1 en_fanin7 .(fan in 7 enable bit) if vidbsel = 0, setting to 1 will enable fanin7 monitor. setting to 0 enables pin 53 with processor b vid bit 4(vidbsel = 1) 0 en_fanin6 .(fan in 6 enable bit) if vidbsel = 0, setting to 1 will enable fanin6 monitor. setting to 0 enables pin 51 with processor b vid bit2(vidbsel = 1) 8.7.2.3 fanin input pin redi rection register(fanin_sel) location : bank 0 address 5d hex type : read / write reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set. fanin_sel bit 7 6 5 4 3 2 1 0 name reserved fanin12sel fanin11sel fanin10sel fanin9sel reset 0 0 0 0 0 0 0 0
W83793G - 40 - bit description 7-4 reserve. 3 fanin12sel. if fanin12sel is set to 0, connecting faniin12 to pin 40; else connect fanin9 to pin 11. while faniin12 connect to pin 11, bank0 cr58 bit0 fan8sel must set to 1. 2 fanin11sel. if fanin11sel is set to 0, connecting faniin11 to pin 39; else connect fanin11 to pin 54. while faniin11 connect to pin 54, bank0 cr58 bit7 vidbsel must set to 0. 1 fanin10sel. if fanin10sel is set to 0, connecting faniin10 to pin 38; else connect fanin10 to pin 52. while faniin10 connect to pin 52, vidbsel must set to 0. 0 fanin9sel. if fanin9sel is set to 0, connecting faniin9 to pi n 37; else connect fanin9 to pin 50. while faniin9 connect to pin 50, vidbsel must set to 0. 8.8 temperature sensors control register W83793G provides two sets of lm75-like sens ors, and they can be treated as two independent sensors through different i 2 c address access(90 hex ~ 9e hex ). two sensor can also be accessed and controlled from W83793G address(58 hex ~ 5e hex ). here lists the control registers for the lm75-like sensors. 8.8.1 temperature sensors control register map mnemonic register name type td1_config. temperature sensor td1 configuration (lm75a) r/w td2_config. temperature sensor td2 configuration (lm75b) r/w td_md temperature sensor mode select 1 r/w tr_md temperature sensor mode select 2 r/w tempoffeset temperature channel offset r/w 8.8.2 temperature sensors control register details 8.8.2.1 td1 configuration (l m75a) register (td1_config) location : bank 0 address 5a hex type : read / write reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set,
W83793G publication release date: dec. 11, 2006 - 41 - revision 1.0 vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set. td1_config bit 7 6 5 4 3 2 1 0 name reserve faultq1 reserve stop1 reset 0 0 00 0 0 0 0 bit description 7-6 reserved. 5-4 faultq1. number of faults to detect before setting ovt# output to avoid false tripping due to noise. 3-1 reserved. 0 stop1. if temperature sensor td1 is set as internal temperatur e sensor (cr5d), set to 1 the temperature sensor will stop monitor. 8.8.2.2 td2 configuration (l m75b) register (td2_config) location : bank 0 address 5b hex type : read / write reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set. td2_config bit 7 6 5 4 3 2 1 0 name reserve faultq2 reserve stop2 reset 0 0 00 0 0 0 0 bit description 7-6 reserved. 5-4 faultq2. number of faults to detect before setting ovt# output to avoid false tripping due to noise. 3-1 reserved. 0 stop2. if temperature sensor td2 is set as internal temperatur e sensor (cr5d), set to 1 the temperature sensor will stop monitor.
W83793G - 42 - 8.8.2.3 td mode select register (td_md) before enable monitor, it needs to set function of pins (bank0.cr58) and sensor select (bank0.cr5e) to correct value. location : td_md - bank 0 address 5e hex type : read / write reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set. td_md bit 7 6 5 4 3 2 1 0 name td4_md td3_md td2_md td1_md reset 01 01 01 01 bit description 7-6 td4_md. temperature d4 mode 00 bin : temperature d4 stop monitor 01 bin : temperature d4 start monitor using internal temperature sensor (default). 10 bin : reserved. 11 bin : temperature d4 start monitor using temperature sensor in intel cpu and get result by peci. 5-4 td3_md. temperature d3 mode 00 bin : temperature d3 stop monitor 01 bin : temperature d3 start monitor using internal temperature sensor (default). 10 bin : reserved. 11 bin : temperature d3 start monitor using temperature sensor in intel cpu and get result by peci. 3-2 td2_md. temperature d2 mode 00 bin : temperature d2 stop monitor 01 bin : temperature d2 start monitor using in ternal temperature sensor (default). 10 bin :. reserved. 11 bin : temperature d2 start monitor using te mperature sensor in intel cpu and get result by peci.
W83793G publication release date: dec. 11, 2006 - 43 - revision 1.0 continued. bit description 1-0 td1_md. temperature d1 mode 00 bin : temperature d1 stop monitor 01 bin : temperature d1 start monitor using internal temperature sensor (default). 10 bin : reserved. 11 bin : temperature d1 start monitor using temperature sensor in intel cpu and get result by peci. 8.8.2.4 tr mode select register (tr_md) location : tr_md - bank 0 address 5f hex type : read / write reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set. tr_md bit 7 6 5 4 3 2 1 0 name reserve tr2_md tr1_md reset 0 0 0 0 0 0 1 1 bit description 7-2 reserve. 1 tr2_md. setting to 1 will enable temperature sensor tr2 monitor. 0 tr1_md. setting to 1 will enable temperature sensor tr1 monitor. 8.8.2.5 temperature channel offset register (tempoffset) each temperature channel has a corresponding offset r egister, in some situation customer may want to shift the offset. default is 00 hex . location : td1offset - bank 0 address a8 hex td2offset - bank 0 address a9 hex td3offset - bank 0 address aa hex
W83793G - 44 - td4offset - bank 0 address ab hex tr1offset - bank 0 address ac hex tr2offset - bank 0 address ad hex type : read / write reset : vsb5v(pin 7) rising. td/troffset bit 7 6 5 4 3 2 1 0 name sign offset value reset 0 0 0 0 0 0 1 1 bit description 7-0 td1~tr2 offset value. 8.9 voltage channel registers here, both monitored value and their corresponding lim itation settings are listed. W83793G provides more detailed resolution for vcorea, vcoreb, and vtt channels, besides 8-bit readout, they have lower-bit can be read. 8.9.1 voltage channel registers map 8.9.1.1 voltage channel monitor value register map mnemonic register name type vcorea. vcorea readout ro vcoreb. vcoreb readout ro vtt. vtt readout ro vinlowb. vin low bit readout ro vsen1. vsen1 readout ro vsen2. vsen2 readout ro 3vsen. 3vsen readout ro 12vsen. 12vsen readout ro 5vdd. 5vdd readout ro 5vsb. 5vsb readout ro vbat. vbat readout ro
W83793G publication release date: dec. 11, 2006 - 45 - revision 1.0 8.9.1.2 voltage channel limit value registers map mnemonic register name type vcorea hl/ll. vcorea high/low limit r/w vcoreb hl/ll. vcoreb high/low limit r/w vtt hl/ll. vtt high/low limit r/w vinhllowb. vin high limit low bit r/w vinlllowb. vin low limit low bit r/w vsen1 hl/ll. vsen1 high/low limit r/w vsen2 hl/ll. vsen2 high/low limit r/w 3vsen hl/ll. 3vsen high/low limit r/w 12vsen hl/ll. 12vsen high/low limit r/w 5vdd hl/ll. 5vdd high/low limit r/w 5vsb hl/ll. 5vsb high/low limit r/w vbat hl/ll. vbat high/low limit r/w 8.9.2 voltage channel register details 8.9.2.1 voltage channel monitored value location : vcorea readout - bank 0 address 10 hex vcoreb readout - bank 0 address 11 hex vtt readout - bank 0 address 12 hex vin low bit - bank 0 address 1b hex vsen1 readout - bank 0 address 14 hex vsen2 readout - bank 0 address 15 hex 3vsen readout - bank 0 address 16 hex 12vsen readout - bank 0 address 17 hex 5vdd readout - bank 0 address 18 hex 5vsb readout - bank 0 address 19 hex vbat readout - bank 0 address 1a hex type : read only reset : no reset
W83793G - 46 - voltage readout bit 7 6 5 4 3 2 1 0 name voltage voltage vin low bit readout bit 7 6 5 4 3 2 1 0 name reserve vttl vcorebl vcoreal channel vcorea/b, and vtt combined two registers fo r each channel to express their monitor result, and so it is 10-bit format data. for example, moni tored value of vcorea can get from combination of vcorea readout and vin low bit readout bit1~0. in or der to read the correct monitor result, it needs to read high byte first than to read its corre sponding low byte. the real voltage calculation of these three channels should follow the formula vcore a voltage = (cr [10]*4 + cr [1b] &0x03) * 0.002; vcore b voltage = (cr [11]*4 + (cr [1b] &0x0c)/4) * 0.002; vtt voltage = (cr [12]*4 + (cr [1b] &0x30)/16) * 0.002; the rest of voltage channels only supply 8-bit output format. the real voltage calculation of these three channels should follow the formula vsen1 voltage = cr [14] * (2 * 0.008); vsen2 voltage = cr [15] * (2 * 0.008); 3vsen voltage = cr [16] * (2 * 0.008); 12vsen voltage = cr [17] * 0.008; 5vdd voltage = cr [18] * (2 * 1.5 * 0.008)+0.15; 5vsb voltage = cr [19] * (2 * 1.5 * 0.008)+0.15; vbat voltage = cr [1a] * (2 * 0.008); 8.9.2.2 voltage channel limitation registers location : vcorea high limit bank 0 address 60 hex vcorea low limit bank 0 address 61 hex vcoreb high limit bank 0 address 62 hex vcoreb low limit bank 0 address 63 hex vtt high limit bank 0 address 64 hex vtt low limit bank 0 address 65 hex high limit low bit bank 0 address 68 hex low limit low bit bank 0 address 69 hex vsen1 high limit bank 0 address 6a hex vsen1 low limit bank 0 address 6b hex vsen2 high limit bank 0 address 6c hex vsen2 low limi bank 0 address 6d hex
W83793G publication release date: dec. 11, 2006 - 47 - revision 1.0 3vsen high limit bank 0 address 6e hex 3vsen low limit bank 0 address 6f hex 12vsen high limit bank 0 address 70 hex 12vsen low limit bank 0 address 71 hex 5vdd high limit bank 0 address 72 hex 5vdd low limit bank 0 address 73 hex 5vsb high limit bank 0 address 74 hex 5vsb low limit bank 0 address 75 hex vbat high limit bank 0 address 76 hex vbat low limit bank 0 address 77 hex type : read / write reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set. voltage high limit bit 7 6 5 4 3 2 1 0 name voltage high limit reset ff hex voltage low limit bit 7 6 5 4 3 2 1 0 name voltage low limit reset 00 hex vin high limit low bit bit 7 6 5 4 3 2 1 0 name reserve vtthll vcorebhll vcoreahll reset 00 11 11 11 vin low limit low bit bit 7 6 5 4 3 2 1 0 name reserve vttlll vcoreblll vcorealll reset 00 00 00 00 the code calculation of high/low limit should follow the formula vcorea, vcoreb, vtt limit setup cr60~66 = [desired voltage]/0.008; cr68/69 = ([desired voltage]/0.002) ? cr60~67 * 4;
W83793G - 48 - vsen1, vsen2, 3vsen limit setup cr6a~6f = [desired voltage] / 0.016; 12vsen limit setup cr70~71 = [desired voltage] / 0.08; 5vdd, 5vsb limit setup cr72~75 = [desired voltage] / 0.024; vbat limit setup cr76~77 = [desired voltage] / 0.016; 8.10 temperature channel registers 8.10.1 temperature channel register map 8.10.1.1 temperature channel monitored value register map mnemonic register name type td1. temperature sensor td1 readout ro td2. temperature sensor td2 readout ro td3. temperature sensor td3 readout ro td4. temperature sensor td4 readout ro tdlowb. temperature sensor td low bit readout ro tr1. temperature sensor tr1 readout ro tr2. temperature sensor tr2 readout ro 8.10.1.2 temperature channel limitation value register map mnemonic register name type td1 ct/cth. td1 critical temperature / critical temperature hysteresis r/w td1 wt/wth. td1 warning temperature / warning temperature hysteresis r/w td2 ct/cth. td2 critical temperature / critical temperature hysteresis r/w td2 wt/wth. td2 warning temperature / warning temperature hysteresis r/w td3 ct/cth. td3 critical temperature / critical temperature hysteresis r/w td3 wt/wth. td3 warning temperature / warning temperature hysteresis r/w td4 ct/cth. td4 critical temperature / critical temperature hysteresis r/w td4 wt/wth. td4 warning temperature / warning temperature hysteresis r/w tr1 ct/cth. tr1 critical temperature / critical temperature hysteresis r/w
W83793G publication release date: dec. 11, 2006 - 49 - revision 1.0 continued. mnemonic register name type tr1 wt/wth. tr1 warning temperature / warning temperature hysteresis r/w tr2 ct/cth. tr2 critical temperature / critical temperature hysteresis r/w tr2 wt/wth. tr2 warning temperature / warning temperature hysteresis r/w 8.10.2 temperature channel register details 8.10.2.1 temperature channel monitored registers location : td1 readout - bank 0 address 1c hex td2 readout - bank 0 address 1d hex td3 readout - bank 0 address 1e hex td4 readout - bank 0 address 1f hex low bit readout - bank 0 address 22 hex tr1 readout - bank 0 address 20 hex tr2 readout - bank 0 address 21 hex type : read only temp readout bit 7 6 5 4 3 2 1 0 name temperature td low bit readout bit 7 6 5 4 3 2 1 0 name td4l td3l td2l td1l the format of temperature channel readout is 2?co mplement. td channel express temperature using 10-bit data including 1-bit sign bit, 7-bit integer, and 2 bits decimal. tr channel express temperature using 8-bit data including 1-bit sign bit, and 7-bit integer. for td channel temperature = tdx + tdxl* 0.25 tr channel temperature = trx
W83793G - 50 - 8.10.2.2 temperature channel limitation registers location: td1 critical - bank 0 address 78 hex td1 critical hystersis - bank 0 address 79 hex td1 warning - bank 0 address 7a hex td1 warning hystersis - bank 0 address 7b hex td2 critical - bank 0 address 7c hex td2 critical hystersis - bank 0 address 7d hex td2 warning - bank 0 address 7e hex td2 warning hystersis - bank 0 address 7f hex td3 critical - bank 0 address 80 hex td3 critical hystersis - bank 0 address 81 hex td3 warning - bank 0 address 82 hex td3 warning hystersis - bank 0 address 83 hex td4 critical - bank 0 address 84 hex td4 critical hystersis - bank 0 address 85 hex td4 warning - bank 0 address 86 hex td4 warning hystersis - bank 0 address 87 hex tr1 critical - bank 0 address 88 hex tr1 critical hystersis - bank 0 address 89 hex tr1 warning - bank 0 address 8a hex tr1 warning hystersis -bank 0 address 8b hex tr2 critical - bank 0 address 8c hex tr2 critical hystersis - bank 0 address 8d hex tr2 warning - bank 0 address 8e hex tr2 warning hystersis - bank 0 address 8f hex type: read / write reset: vsb5v (pin 7) rising. sensor critical temperature bit 7 6 5 4 3 2 1 0 name temp critical temperature reset 64 hex (100 c)
W83793G publication release date: dec. 11, 2006 - 51 - revision 1.0 sensor critical temperature hystersis bit 7 6 5 4 3 2 1 0 name sensor critical temperature hysteresis reset 5f hex (95 c) sensor critical temperature bit 7 6 5 4 3 2 1 0 name sensor warning temperature reset 55 hex (85 c) sensor warning temperature hystersis bit 7 6 5 4 3 2 1 0 name sensor warning temperature hysteresis reset 50 hex (80 c) the format of temperature channel limit is 2?complement, bit 7 is sign bit, range is ?128~127. 8.11 fan control registers all fan control/status register are allocated in bank 0 and bank 2. bank 0 resides common-used control/status registers, and bank 2 inside has smart fan control setups. 8.11.1 fan register map 8.11.1.1 common register cont rol/status registers block all common fan control/status r egisters are located in bank 0.
W83793G - 52 - here listed registers which can read out tachometer va lues, and their limit regist ers. all these registers are separated into 2 bytes. reading tachometer c ount high byte will lock the corresponding low byte to ensure next reading on low byte will get consistent data with high byte. due to fan input 6~12 are multifunction pins, fanincontrol provides selection between fanin functions or other functions. also here provides fan output style(dc/ pwm), duty cycle, and frequency controls. 8.11.1.2 smart fan setup/status registers registers of smartfan setup resides in bank 0 and bank 2. most used step timing control and critical temperature setup are located in bank 0, all others located in bank 2. mnemonic register name type fan1counth/l. | fan12counth/l. fan tachometer readout high/low byte ro fan1limith/l. | fan12limith/l. fan count limit high/low byte rw fanctrl1. fanctrl2. fan output style control rw defaultspeed. default fan speed at power-on rw fan1duty. | fan8duty. current fan output duty cycle rw pwm1prescalar. | pwm8prescalar. fan pwm output frequency pre-scalar rw
W83793G publication release date: dec. 11, 2006 - 53 - revision 1.0 smart fan mode is activated on corresponding fan once users define their relationship with temperature input in tempfanselect. under sm artfan mode, user can select thermal cruise mode or smart fan ii mode by assigning fanctrlmode. tempfanselect enables users to arbitrarily define the tem perature-to-fan relationship. for example, one can define thermistor input 1 as chassis tem perature sensor, and temperature 1(diode input 1) as cpu sensor. user can do following manipulati on to the fan1(cpu fan) and fan2(system fan). assigning td1fanselect 03 hex and tr1fanselect 02 hex , W83793G will associate the system fan with cpu sensor and chassis sensor, but cpu fan only affects by cpu sensor. more descriptions can be found at the register defin ition section for this issue. under smartfan mode, a specific temperature will be defined in criticaltemp , when any temperature input detected temperature higher than this will c ause all fan to full speed simultaneously. beside this, in normal use several control parameters can be defined in following graph. mnemonic register name type uptime. smartfan fan step up time rw downtime. smartfan fan step down time rw criticaltemp. all fan full speed temperature rw td1fanselect. tr2fanselect. temperature to fan mapping relationships in smartfan mode rw fanctrlmode. smartfan control mode select rw toltd12. toltr12. hysteresis tolerance of each temperature source rw fan1nonstop. fan8nonstop. fan output nonstop duty cycle rw fan1start. fan8start. fan output start duty cycle rw fan1stoptime. fan8stoptime. fan stop time from nonstop level to turn off. rw
W83793G - 54 - 8.11.1.3 thermal cruise mode registers(bank 2) thermal cruise mode is an algorithm to control fan speed to keep the temperature source around the target temperature. if the temperature source detec ts temperatures higher or lower than target with toltemp tolerance, smart fan control will take actions to speed up or lower down the fan to keep the temperature within the tolerance range. temperature toltemp toltemp mnemonic register name type td1target. tr2target. target temperature of temperature inputs rw
W83793G publication release date: dec. 11, 2006 - 55 - revision 1.0 the concept is quite simple, when tem perature is larger(not include equal) than targettemp + toltemp , fan will speed up; when temperature is less(not include equal) than targettemp - toltemp , fan will slow down; otherwise, fan keeps its current speed. 8.11.1.4 smart fan ii control registers(bank 2) smart fan ii algorithm provides user a mechani sm to setup fan speed via temperature level relationship. each temperature source has a corre sponding table, and totally six tables are used to control temperature 1(d1) to temperature 6 (r2). a table is consisted of 7 temperature levels and 7 fan levels as following. templevel01 templevel12 templevel23 templevel34 templevel45 templevel56 templevel67 while fan speed jump from one level to another level, there is a hysterisis me chanism to prevent fan from throttling. when speed jump high to another leve l, temperature need to at specified temperature level, but instead when speed is slow down, it must wait until temperature is lower than specified temperature level minus tolerance. mnemonic register name type td1level01. tr2level67. smart fan ii fan transition temperature levels rw td1fanlevel0. tr2fanlevel6. smart fan ii fan output levels rw
W83793G - 56 - 8.11.2 fan register details 8.11.2.1 fan tachometer readout hi gh/low byte register(fancounth/l) the fancounth/l maintains current count value of corresponding fan inputs. when vsb 5v power on, it is cleared(00 hex ). effective width of fancounth/l is 12- bits, fancounth high nibble is not used. location : fan1counth - bank 0 address 23 hex fan1countl ? bank 0 address 24 hex fan2counth ? bank 0 address 25 hex fan2countl ? bank 0 address 26 hex fan3counth ? bank 0 address 27 hex fan3countl ? bank 0 address 28 hex fan4counth ? bank 0 address 29 hex fan4countl ? bank 0 address 2a hex fan5counth ? bank 0 address 2b hex fan5countl ? bank 0 address 2c hex fan6counth ? bank 0 address 2d hex fan6countl ? bank 0 address 2e hex fan7counth ? bank 0 address 2f hex fan7countl ? bank 0 address 30 hex fan8counth ? bank 0 address 31 hex fan8countl ? bank 0 address 32 hex fan9counth ? bank 0 address 33 hex fan9countl ? bank 0 address 34 hex fan10counth ? bank 0 address 35 hex fan10countl ? bank 0 address 36 hex fan11counth ? bank 0 address 37 hex fan11countl ? bank 0 address 38 hex fan12counth ? bank 0 address 39 hex fan12countl ? bank 0 address 3a hex type : read only reset : vsb5v(pin 7) rising fan1counth~fan12counth bit 7 6 5 4 3 2 1 0 name fancounth reset 00 hex
W83793G publication release date: dec. 11, 2006 - 57 - revision 1.0 bit description 7-0 fancounth (fan tachometer readout high byte). the count value high byte of fanin signal period with 45khz clock. fan1countl~fan12countl bit 7 6 5 4 3 2 1 0 name fancountl reset 00 hex bit description 7-0 fancountl (fan tachometer readout low byte). the count value low byte of fanin signal period with 45khz clock. fan count calculation fan1countl combined with fan1counth forms the 12- bit count value. if reading the fan1counth and fan1countl successively, W83793G will make these tw o count value consistent( i.e. the same counting). if user read them in reverse order or ot her read/write between them, it is possible that the high/low byte may come from different counting and leads to some abnormal reading. same rules can be applied to other fancounts. real rpm(rotate per minute) calculations should follow the formula ) 4 ( ) 12 ( 10 35 . 1 ) ( 6 fanpoles lue bitcountva rpm speed fan ? = in this formula, 12-bitcountvalue represents the values st ored in the fancounth/l, and fanpoles stands for the number of ns poles pair inside the fan, normally a n-s-n-s fan( fanpoles = 4) will generate 2 pulses when complete one rotate. fan tachometer normal operating range is below 4. 5khz(if fanpoles=4, it means 135krpm), nearly impossible but a fan rotating faster t han this will cause W83793G works abnormally. 8.11.2.2 fan count limit high/low byte(fanlimith/l) the fanlimith/l setups the limit range for fan in count va lues, if counter counts value larger than these register indicates, W83793G will show alert in real-time status and may take further actions based on user setups. while reset it is set(ff hex ). location : fan1limith - bank 0 address 90 hex fan1limitl ? bank 0 address 91 hex fan2limith ? bank 0 address 92 hex fan2limitl ? bank 0 address 93 hex fan3limith ? bank 0 address 94 hex fan3limitl ? bank 0 address 95 hex
W83793G - 58 - fan4limith ? bank 0 address 96 hex fan4limitl ? bank 0 address 97 hex fan5limith ? bank 0 address 98 hex fan5limitl ? bank 0 address 99 hex fan6limith ? bank 0 address 9a hex fan6limitl ? bank 0 address 9b hex fan7limith ? bank 0 address 9c hex fan7limitl ? bank 0 address 9d hex fan8limith ? bank 0 address 9e hex fan8limitl ? bank 0 address 9f hex fan9limith ? bank 0 address a0 hex fan9limitl ? bank 0 address a1 hex fan10limith ? bank 0 address a2 hex fan10limitl ? bank 0 address a3 hex fan11limith ? bank 0 address a4 hex fan11limitl ? bank 0 address a5 hex fan12limith ? bank 0 address a6 hex fan12limitl ? bank 0 address a7 hex type : read / write reset : vsb5v(pin 7) rising. fan1limith ~ fan12limith bit 7 6 5 4 3 2 1 0 name fanlimith reset ff hex bit description 7-0 fanlimith (fan tachometer limit high byte). the limitat ion of count value high byte of fanin. fan1limitl~fan12limitl bit 7 6 5 4 3 2 1 0 name fanlimitl reset ff hex
W83793G publication release date: dec. 11, 2006 - 59 - revision 1.0 bit description 7-0 fanlimitl (fan tachometer readout limit low byte). the limitation count value low byte of fanin. 8.11.2.3 fan output style control (fanctrl) the fanctrl1/2 decides the fan output style. ther e are several output styles available in W83793G, which are od mode(open-drain), ob mode(ouput -buffer), and dc mode(dac output). default all fans outputs are set to od mode. location : fanctrl1 - bank 0 address b0 hex fanctrl2 ? bank 0 address b1 hex type : read / write reset : . vsb5v(pin 7) rising, init reset(cr40.bit7) is set, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set. fanctrl1 bit 7 6 5 4 3 2 1 0 name f8ob f7ob f6ob f5ob f4ob f3ob f2ob f1ob reset 0 0 0 0 0 0 0 0 bit description 7 f8ob (fan output 8 output buffer mode control). 0: depends on f8dc (crb1.bit7), if f8dc=1, pin 11 out put with dc mode. otherwise output is configured with od mode. 1: depends on f8dc (crb1.bit7), if f8dc=1, pin 11 out put with dc mode. otherwise output is configured with ob mode 6 f7ob (fan output 7 output buffer mode control). 0: depends on f7dc (crb1.bit6), if f7dc=1, pin 54 out put with dc mode. otherwise output is configured with od mode. 1: depends on f7dc (crb1.bit6), if f7dc=1, pin 54 out put with dc mode. otherwise output is configured with ob mode 5 f6ob (fan output 6 output buffer mode control). 0: depends on f6dc (crb1.bit5), if f6dc=1, pin 52 out put with dc mode. otherwise output is configured with od mode. 1: depends on f6dc (crb1.bit5), if f6dc=1, pin 52 out put with dc mode. otherwise output is configured with ob mode
W83793G - 60 - continued. bit description 4 f5ob (fan output 5 output buffer mode control). 0: depends on f5dc (crb1.bit4), if f5dc=1, pin 50 output with dc mode. otherwise output is configured with od mode. 1: depends on f5dc (crb1.bit4), if f5dc=1, pin 50 output with dc mode. otherwise output is configured with ob mode 3 f4ob (fan output 4 output buffer mode control). 0: depends on f4dc (crb1.bit3), if f4dc=1, pin 49 output with dc mode. otherwise output is configured with od mode. 1: depends on f4dc (crb1.bit3), if f4dc=1, pin 49 output with dc mode. otherwise output is configured with ob mode 2 f3ob (fan output 3 output buffer mode control). 0: depends on f3dc (crb1.bit2), if f3dc=1, pin 46 output with dc mode. otherwise output is configured with od mode. 1: depends on f3dc (crb1.bit2), if f3dc=1, pin 46 output with dc mode. otherwise output is configured with ob mode 1 f2ob (fan output 2 output buffer mode control). 0: depends on f2dc (crb1.bit1), if f2dc=1, pin 44 output with dc mode. otherwise output is configured with od mode. 1: depends on f2dc (crb1.bit1), if f2dc=1, pin 44 output with dc mode. otherwise output is configured with ob mode 0 f1ob (fan output 1 output buffer mode control). 0: depends on f1dc (crb1.bit0), if f1dc=1, pin 42 output with dc mode. otherwise output is configured with od mode. 1: depends on f1dc (crb1.bit0), if f1dc=1, pin 42 output with dc mode. otherwise output is configured with ob mode fanctrl2 bit 7 6 5 4 3 2 1 0 name f8dc f7dc f6dc f5dc f4dc f3dc f2dc f1dc reset 0 0 0 0 0 0 0 0 bit description 7 f8dc (fan output 8 direct current mode control). 0: od or ob mode on pin 11. depend on f8ob (crb0.bit7) 1: pin 11 set as dc mode.
W83793G publication release date: dec. 11, 2006 - 61 - revision 1.0 continued. bit description 6 f7dc (fan output 7 direct current mode control). 0: od or ob mode on pin 54. depend on f7ob (crb0.bit6) 1: pin 54 set as dc mode. 5 f6dc (fan output 6 direct current mode control). 0: od or ob mode on pin 52. depend on f6ob (crb0.bit5) 1: pin 52 set as dc mode. 4 f5dc (fan output 5 direct current mode control). 0: od or ob mode on pin 50. depend on f5ob (crb0.bit4) 1: pin 50 set as dc mode. 3 f4dc (fan output 4 direct current mode control). 0: od or ob mode on pin 49. depend on f4ob (crb0.bit3) 1: pin 49 set as dc mode. 2 f3dc (fan output 3 direct current mode control). 0: od or ob mode on pin 46. depend on f3ob (crb0.bit2) 1: pin 46 set as dc mode. 1 f2dc (fan output 2 direct current mode control). 0: od or ob mode on pin 44. depend on f2ob (crb0.bit1) 1: pin 44 set as dc mode. 0 f1dc (fan output 1 direct current mode control). 0: od or ob mode on pin 42. depend on f1ob (crb0.bit0) 1: pin 42 set as dc mode. 8.11.2.4 default fan speed at power-on (defaultspeed) defaultspeed set the initial speed of every fan. when system is turned on, all fans output will be set a default duty as this register content. this register?s reset is specially design to be reset by vsb only, so at second system power on, the system will use the lastest setup speed to turn on all fans. location : defaultspeed - bank 0 address b2 hex type : read / write reset : vsb5v(pin 7) rising.
W83793G - 62 - defaultspeed bit 7 6 5 4 3 2 1 0 name reserved defaultspeed reset 0 0 30 hex bit description 7-6 reserved. 5-0 defaultspeed (default fan speed at power-on). specif ies the fan duty at next power on. 8.11.2.5 current fan output duty cycle (fanduty) fanduty reflects the current output duty cycle. in manual mode it also can be set user desired duty cycles. but in smart fan mode, it is read-only. location : fan1duty - bank 0 address b3 hex fan2duty - bank 0 address b4 hex fan3duty - bank 0 address b5 hex fan4duty - bank 0 address b6 hex fan5duty - bank 0 address b7 hex fan6duty - bank 0 address b8 hex fan7duty - bank 0 address b9 hex fan8duty - bank 0 address ba hex type : read / write(only in manual mode, make sure 5vdd and pin 1 clk is ready) reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set. fan1duty ~ fan8duty bit 7 6 5 4 3 2 1 0 name reserved fanduty reset 0 0 depend on defaultspeed . bit description 7-6 reserved. 5-0 fanduty (current fan output duty cycle). specifie s the current fan output duty cycle. while vdd5v is low, this register is forcing to be zero by hardware.
W83793G publication release date: dec. 11, 2006 - 63 - revision 1.0 fanduty also has a special charac teristic; it?s called sequential powe r-on. this function is used to avoid system current ove r-load while system power-on and all fans start to spin. W83793G will turn on each fan in sequence and it take 0.1sec to pow er on all fans.(12.5ms intervals for 8 fans) 8.11.2.6 fan pwm output frequency prescalar (pwmprescalar) pwmprescalar controls the output frequency in pw m mode. here a large range of clock can be selected to fit customer needs. default output frequency is 25khz. location : pwm1prescalar - bank 0 address bb hex pwm2prescalar - bank 0 address bc hex pwm3prescalar - bank 0 address bd hex pwm4prescalar - bank 0 address be hex pwm5prescalar - bank 0 address bf hex pwm6prescalar - bank 0 address c0 hex pwm7prescalar - bank 0 address c1 hex pwm8prescalar - bank 0 address c2 hex type : read / write(only in manual mode) reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set. pwm1prescalar ~ pwm8prescalar bit 7 6 5 4 3 2 1 0 name cksel divisor reset 1 09 hex bit description 7 cksel (clock source select). 0: 512hz. 1: 250khz. 6-0 divisor (clock divisor). clock frequency divisor. the clock source selected by cksel will be di vided by divisor and used as a fan pwm output frequency. there are 2 cases of divisor depends on cksel. if cksel equals 1, then output clock is simply equals to 250/(divisor+1) khz. if cksel equals 0, output clock is 512hz/mappeddiv isor. mappeddivisor depends on divisor[3:0] and looks like below table.
W83793G - 64 - divisor[3:0] mapped divisor output frequency divisor[3:0] mapped divisor output frequency 0000 1 512hz 1000 12 43hz 0001 2 256hz 1001 16 32hz 0010 3 171hz 1010 32 16hz 0011 4 128hz 1011 64 8hz 0100 5 102hz 1100 128 4hz 0101 6 85hz 1101 256 2hz 0110 7 73hz 1110 512 1hz 0111 8 64hz 1111 1024 0.5hz 8.11.2.7 smartfan output step up time (uptime) uptime regulates the time interval of fast est fan speed up a unit. default setting is 0.6sec. location : uptime - bank 0 address c3 hex type : read / write reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set. uptime bit 7 6 5 4 3 2 1 0 name uptime reset 06 hex bit description 7-0 uptime (smartfan step up time). unit in 0.1sec. programmed as the interval of continuous fan ramping up. smartfan mostly control fans smoothly, which m eans it seldom suddenly add a large duty to fan or decrease a large duty. instead, most often it incr ease/decrease duty by 1 lsb one time. the up time / down time register defines the time interval between successively increase/decrease duty. if this value set too small, fan will have no time to re flect the speed after tuning the duty and sometimes may cause fan speed unstable; on the other hand, if se t up time / down time too large, fan may not act fast enough to dissipate the heat. this register should never set to 0 , otherwise will cause fan duty abnormal. only in these cases, fan will suddenly jump large duty. ? vdd power ? on/off
W83793G publication release date: dec. 11, 2006 - 65 - revision 1.0 ? critical temperature reached ? fan turn off state to start ? fan at nonstop level to turn off state 8.11.2.8 smartfan output step down time (downtime) down time regulates the time interval of fastes t fan speed lowered a unit. default setting is 0.6sec. location : downtime - bank 0 address c4 he xtype : read / write reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set. downtime bit 7 6 5 4 3 2 1 0 name downtime reset 06 hex bit description 7-0 downtime (smartfan step down time). unit in 0. 1sec. programmed as the interval of continuous fan ramping down. this register should never set to 0 , otherwise will cause fan duty abnormal. 8.11.2.9 all fan full speed temperature (criticaltemp) criticaltemp defines a system critical temperature wh ile exceeding this temperature may lead to system damage or crash. when W83793G det ects any temperature input exceeding criticaltemp , it will speed all fans and try to lowering the temperature. location : critcaltemp - bank 0 address c5 hex type : read / write reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set. uptime bit 7 6 5 4 3 2 1 0 name reserved criticaltemp reset 0 50 hex
W83793G - 66 - bit description 7 reserved. 6-0 criticaltemp (all fan full speed temperature). 8.11.2.10 temperature to fan mapping re lationships register (tempfanselect) the tempfanselect is responsible for dealing with the relationship between fan and temperature source. while reset it is cleared(00 hex ). location : td1fanselect - bank 2 address 01 hex td2fanselect - bank 2 address 02 hex td3fanselect - bank 2 address 03 hex td4fanselect - bank 2 address 04 hex tr1fanselect - bank 2 address 05 hex tr2fanselect - bank 2 address 06 hex type : read / write reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set. td1fanselect ~ tr2fanselect bit 7 6 5 4 3 2 1 0 name fan8 fan7 fan6 fan5 fan4 fan3 fan2 fan1 reset 0 0 0 0 0 0 0 0 bit description 7 fan8 (enable fan8 smart fan). 0: fan8 has no relation with this temperature source. 1: applies smartfan control on fan8 and this temperature. 6 fan7 (enable fan7 smart fan). 0: fan7 has no relation with this temperature source. 1: applies smartfan control on fan7 and this temperature. 5 fan6 (enable fan6 smart fan). 0: fan6 has no relation with this temperature source. 1: applies smartfan control on fan6 and this temperature.
W83793G publication release date: dec. 11, 2006 - 67 - revision 1.0 continued. bit description 4 fan5 (enable fan5 smart fan). 0: fan5 has no relation with this temperature source. 1: applies smartfan control on fan5 and this temperature. 3 fan4 (enable fan4 smart fan). 0: fan4 has no relation with this temperature source. 1: applies smartfan control on fan4 and this temperature. 2 fan3 (enable fan3 smart fan). 0: fan3 has no relation with this temperature source. 1: applies smartfan control on fan3 and this temperature. 1 fan2 (enable fan2 smart fan). 0: fan2 has no relation with this temperature source. 1: applies smartfan control on fan2 and this temperature. 0 fan1 (enable fan1 smart fan). 0: fan1 has no relation with this temperature source. 1: applies smartfan control on fan1 and this temperature. here using an example to explain the concept of tempfanselect mapping. considering this case, td1fanselect is set to 86 hex , td2fanselect is set to 52 hex , td3fanselect is set 20 hex , and other 3 left unset. we can spilt the six registers bit by bit as above figure, and give it a rotation, this help us to understand the relationship from the point of fan eas ier. for fan1 and fan4 row, all temperature is de- asserted, that means fan1/fan4 does not have any relationship with te mperature, thus they are in manual mode under this setting. for fan2, it is clear that it has relation with temperature 1 and 2, so it will activate smartfan control with temperature 1/2 as it input.
W83793G - 68 - the right graph give a picture of how the mapping relationship is made by this setting. in this example, fan2 retrieves information from temperature 1 and temperature 2, and decide the next duty cycle applied to fan2. but how did it decide to speed up/slow down fan? basically, W83793G sorting the information comes from each temperature sensor and smartfan controls. after sorting the information, W83793G will get something like, td1 need to speed up fan, and td2 does not need so fast fan speed; or td1 would no more need fast fan, and td2 hopes to keep current fan speed. and after that, the algorithm will make a decision to control fan by a very simple rule, which can expressed very simply in the following. if td1 say, ?i need faster fan?, and td2 says, ?no fast fan needed?. W83793G will take request of td1 and start to speed up fan. in short, W83793G always prefers to pick the most critical request and applies it to the related fan. temperature 1 temperature 2 temperature 3 temperature 4 temperature 5 temperature 6 fan1 fan2 fan3 fan4 fan5 fan6 fan7 fan8 any temp request faster fan?? any temp request f hold current speed?? no no speed up hold current speed slow down yes yes
W83793G publication release date: dec. 11, 2006 - 69 - revision 1.0 8.11.2.11 smartfan control mode select register (fanctrlmode) there are two smartfan modes supported with W83793G once smartfan function enabled (please refer tempfanselect to enable smartfan function), they are thermal cruise mode and smartfan ii mode. while reset it is cleared (00 hex ), smartfan ii mode. location : fanctrlmode - bank 2 address 07 hex type : read / write reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set. fanctrlmode bit 7 6 5 4 3 2 1 0 name reserved tr2_md tr1_md td4_md td3_md td2_md td1_md reset 0 0 0 0 0 0 0 0 bit description 7-6 reserved. 5 tr2_md (thermistor 2 smartfan control mode) 0: smartfan ii mode. 1: thermal cruise mode. 4 tr1_md (thermistor 1 smartfan control mode) 0: smartfan ii mode. 1: thermal cruise mode. 3 td4_md (thermal diode 4 smartfan control mode) 0: smartfan ii mode. 1: thermal cruise mode. 2 td3_md (thermal diode 3 smartfan control mode) 0: smartfan ii mode. 1: thermal cruise mode. 1 td2_md (thermal diode 2 smartfan control mode) 0: smartfan ii mode. 1: thermal cruise mode. 0 td1_md (thermal diode 1 smartfan control mode) 0: smartfan ii mode. 1: thermal cruise mode. 8.11.2.12 hysteresis tolerance of temperature register(toltemp) in smartfan mode, to avoid temperature unstable c ausing fan throttling, W83793G uses a hysteresis temperature to separate the speed up/slow down tem perature point. while reset it is set to 2 (22 hex ). location :
W83793G - 70 - toltd12 - bank 2 address 08 hex toltd34 - bank 2 address 09 hex toltr12 - bank 2 address 0a hex type : read / write reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set. toltd12 bit 7 6 5 4 3 2 1 0 name to l t d 2 to l t d 1 reset 2 hex 2 hex bit description 7-4 toltd2 (td 2 tolerance range). unit in . 3-0 toltd1 (td 1 tolerance range). unit in . toltd34 bit 7 6 5 4 3 2 1 0 name to l t d 4 to l t d 3 reset 2 hex 2 hex bit description 7-4 toltd4 (td 4 tolerance range). unit in . 3-0 toltd3 (td 3 tolerance range). unit in . toltr12 bit 7 6 5 4 3 2 1 0 name to l t r 2 to l t r 1 reset 2 hex 2 hex bit description 7-4 toltr2 (tr2 tolerance range). unit in . 3-0 toltr1 (tr1 tolerance range). unit in .
W83793G publication release date: dec. 11, 2006 - 71 - revision 1.0 8.11.2.13 fan output nonstop duty cycle register(fannonstop) due to bring a fan from stop to work might take some time. the design of fannonstop is hope to have a minimum duty cycle to keep the fan rotating when system does not require fan help getting ride of heat but still want to keep the fast res ponse time to speed up fan. (reference to graph ) location : fan1nonstop - bank 2 address 18 hex fan2nonstop - bank 2 address 19 hex fan3nonstop - bank 2 address 1a hex fan4nonstop - bank 2 address 1b hex fan5nonstop - bank 2 address 1c hex fan6nonstop - bank 2 address 1d hex fan7nonstop - bank 2 address 1e hex fan8nonstop - bank 2 address 1f hex type : read / write reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set. fannonstop bit 7 6 5 4 3 2 1 0 name reserved fannonstop reset 0 4 hex bit description 7-6 reserved. 5-0 fannonstop (fan output nonstop duty cycle). 8.11.2.14 fan output start duty cycle register(fanstart) from still to rotate, fan usually needs a higher duty cycle to generate enough torque to conquer the restriction force. thus W83793G include a fanstart to bring the fan live with the duty specified. (reference to graph ) location : fan1start - bank 2 address 20 hex fan2start - bank 2 address 21 hex fan3start - bank 2 address 22 hex fan4start - bank 2 address 23 hex
W83793G - 72 - fan5start - bank 2 address 24 hex fan6start - bank 2 address 25 hex fan7start - bank 2 address 26 hex fan8start - bank 2 address 27 hex type : read / write reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set. fanstart bit 7 6 5 4 3 2 1 0 name reserved fanstart reset 0 8 hex bit description 7-6 reserved. 5-0 fanstart (fan output start duty cycle). 8.11.2.15 fan output stop time register(fanstoptime) a time interval is specified to tell W83793G when to turn off fan if smartfan continuously request to slower down fan, but fan already reached the nonstop level. default is 10 sec. (reference to graph ) location : fan1stoptime - bank 2 address 28 hex fan2stoptime - bank 2 address 29 hex fan3stoptime - bank 2 address 2a hex fan4stoptime - bank 2 address 2b hex fan5stoptime - bank 2 address 2c hex fan6stoptime - bank 2 address 2d hex fan7stoptime - bank 2 address 2e hex fan8stoptime - bank 2 address 2f hex type : read / write reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set.
W83793G publication release date: dec. 11, 2006 - 73 - revision 1.0 fanstoptime bit 7 6 5 4 3 2 1 0 name fanstoptime reset 64 hex bit description 7-0 fanstoptime (fan stop time from nonstop level to turn off). unit in 0.1sec. ranged from 0.1sec to 25.5sec. if set to 0, fan will never stop. 8.11.2.16 target temperature of temperature inputs register(temptarget) in thermal cruise mode, a target temper ature is needed to be defined for each temperature source. W83793G will try to tune fan speed to keep t he temperature of target device around the target temperature. default target temperature for di ode sensors is 40 , and 32 for thermistor sensors. location : td1target - bank 2 address 10 hex td2target - bank 2 address 11 hex td3target - bank 2 address 12 hex td4target - bank 2 address 13 hex tr1target - bank 2 address 14 hex tr2target - bank 2 address 15 hex type : read / write reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set. td1target ~ td4target bit 7 6 5 4 3 2 1 0 name r e s e r v e d te m p ta r g e t reset 0 28 hex
W83793G - 74 - bit description 7 reserved. 6-0 temptarget . (diode temperature sensor target temperature). unit in tr1target ~ tr2target bit 7 6 5 4 3 2 1 0 name r e s e r v e d te m p ta r g e t reset 0 20 hex bit description 7 reserved. 6-0 temptarget . (thermistor temperature s ensor target temperature). unit in see also : toltemp , fanctrlmode , thermal cruise mode . 8.11.2.17 smart fan ii fan transition temperature level registers (templevel) smartfan ii, an algorithm providing a table mapping me chanism to translate temperature information into output fan duties. the mapping table need user to provide 2 domains for the translation, those are at certain temperature mapping to certain duty. templevel (temperature) and tempfanlevel (duty cycle) are used to define the table. there totally are six tables reside in W83793G, one table per temperature channel; 7 entries per table. therefore here templevel will have 42 registers, and another 42 registers for tempfanlevel in this and next section. location : td1level01 - bank 2 address 30 hex td1level12 - bank 2 address 31 hex td1level23 - bank 2 address 32 hex td1level34 - bank 2 address 33 hex td1level45 - bank 2 address 34 hex td1level56 - bank 2 address 35 hex td1level67 - bank 2 address 36 hex td2level01 - bank 2 address 40 hex td2level12 - bank 2 address 41 hex td2level23 - bank 2 address 42 hex td2level34 - bank 2 address 43 hex td2level45 - bank 2 address 44 hex
W83793G publication release date: dec. 11, 2006 - 75 - revision 1.0 td2level56 - bank 2 address 45 hex td2level67 - bank 2 address 46 hex td3level01 - bank 2 address 50 hex td3level12 - bank 2 address 51 hex td3level23 - bank 2 address 52 hex td3level34 - bank 2 address 53 hex td3level45 - bank 2 address 54 hex td3level56 - bank 2 address 55 hex td3level67 - bank 2 address 56 hex td4level01 - bank 2 address 60 hex td4level12 - bank 2 address 61 hex td4level23 - bank 2 address 62 hex td4level34 - bank 2 address 63 hex td4level45 - bank 2 address 64 hex td4level56 - bank 2 address 65 hex td4level67 - bank 2 address 66 hex tr1level01 - bank 2 address 70 hex tr1level12 - bank 2 address 71 hex tr1level23 - bank 2 address 72 hex tr1level34 - bank 2 address 73 hex tr1level45 - bank 2 address 74 hex tr1level56 - bank 2 address 75 hex tr1level67 - bank 2 address 76 hex tr2level01 - bank 2 address 80 hex tr2level12 - bank 2 address 81 hex tr2level23 - bank 2 address 82 hex tr2level34 - bank 2 address 83 hex tr2level45 - bank 2 address 84 hex tr2level56 - bank 2 address 85 hex tr2level67 - bank 2 address 86 hex type : read / write reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set.
W83793G - 76 - td1level01 ~ tr2level01 bit 7 6 5 4 3 2 1 0 name reserved templevel01 reset 0 1e hex bit description 7 reserved. 6-0 templevel01 . (temperature level between tempfanlevel0 and tempfanlevel1). unit in td1level12 ~ tr2level12 bit 7 6 5 4 3 2 1 0 name reserved templevel12 reset 0 23 hex bit description 7 reserved. 6-0 templevel12 . (temperature level between tempfanlevel1 and tempfanlevel2). unit in td1level23 ~ tr2level23 bit 7 6 5 4 3 2 1 0 name reserved templevel23 reset 0 28 hex bit description 7 reserved. 6-0 templevel23 . (temperature level between tempfanlevel2 and tempfanlevel3). unit in td1level34 ~ tr2level34 bit 7 6 5 4 3 2 1 0 name reserved templevel34 reset 0 2d hex
W83793G publication release date: dec. 11, 2006 - 77 - revision 1.0 bit description 7 reserved. 6-0 templevel34 . (temperature level between tempfanlevel3 and tempfanlevel4). unit in td1level45 ~ tr2level45 bit 7 6 5 4 3 2 1 0 name reserved templevel45 reset 0 32 hex bit description 7 reserved. 6-0 templevel45 . (temperature level between tempfanlevel4 and tempfanlevel5). unit in td1level56 ~ tr2level56 bit 7 6 5 4 3 2 1 0 name reserved templevel56 reset 0 37 hex bit description 7 reserved. 6-0 templevel56 . (temperature level between tempfanlevel5 and tempfanlevel6). unit in td1level67 ~ tr2level67 bit 7 6 5 4 3 2 1 0 name reserved templevel67 reset 0 3c hex
W83793G - 78 - bit description 7 reserved. 6-0 templevel67 . (temperature level between tempfanlevel6 and tempfanlevel7). unit in see also : toltemp , fanctrlmode , smart fan ii mode . 8.11.2.18 smart fan ii fan output levels registers (tempfanlevel) previous section describes one temperature axis of smart fan ii table, here introduced fan duty axis for the table, tempfanlevel registers. location : td1fanlevel0 - bank 2 address 38 hex td1fanlevel1 - bank 2 address 39 hex td1fanlevel2 - bank 2 address 3a hex td1fanlevel3 - bank 2 address 3b hex td1fanlevel4 - bank 2 address 3c hex td1fanlevel5 - bank 2 address 3d hex td1fanlevel6 - bank 2 address 3e hex td2fanlevel0 - bank 2 address 48 hex td2fanlevel1 - bank 2 address 49 hex td2fanlevel2 - bank 2 address 4a hex td2fanlevel3 - bank 2 address 4b hex td2fanlevel4 - bank 2 address 4c hex td2fanlevel5 - bank 2 address 4d hex td2fanlevel6 - bank 2 address 4e hex td3fanlevel0 - bank 2 address 58 hex td3fanlevel1 - bank 2 address 59 hex td3fanlevel2 - bank 2 address 5a hex td3fanlevel3 - bank 2 address 5b hex td3fanlevel4 - bank 2 address 5c hex td3fanlevel5 - bank 2 address 5d hex td3fanlevel6 - bank 2 address 5e hex td4fanlevel0 - bank 2 address 68 hex td4fanlevel1 - bank 2 address 69 hex td4fanlevel2 - bank 2 address 6a hex td4fanlevel3 - bank 2 address 6b hex
W83793G publication release date: dec. 11, 2006 - 79 - revision 1.0 td4fanlevel4 - bank 2 address 6c hex td4fanlevel5 - bank 2 address 6d hex td4fanlevel6 - bank 2 address 6e hex tr1fanlevel0 - bank 2 address 78 hex tr1fanlevel1 - bank 2 address 79 hex tr1fanlevel2 - bank 2 address 7a hex tr1fanlevel3 - bank 2 address 7b hex tr1fanlevel4 - bank 2 address 7c hex tr1fanlevel5 - bank 2 address 7d hex tr1fanlevel6 - bank 2 address 7e hex tr2fanlevel0 - bank 2 address 88 hex tr2fanlevel1 - bank 2 address 89 hex tr2fanlevel2 - bank 2 address 8a hex tr2fanlevel3 - bank 2 address 8b hex tr2fanlevel4 - bank 2 address 8c hex tr2fanlevel5 - bank 2 address 8d hex tr2fanlevel6 - bank 2 address 8e hex type : read / write reset : vsb5v(pin 7) rising, init reset(cr40.bit7) is set, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set, sysrstin_n(pin 15) falling @ sysrst_md(cr40.bit5) set. td1fanlevel0 ~ tr2fanlevel0 bit 7 6 5 4 3 2 1 0 name reserved tempfanlevel0 reset 0 08 hex bit description 7-6 reserved. 5-0 tempfanlevel0 . (fan output level 0).
W83793G - 80 - td1fanlevel1 ~ tr2fanlevel1 bit 7 6 5 4 3 2 1 0 name reserved tempfanlevel1 reset 0 0c hex bit description 7-6 reserved. 5-0 tempfanlevel1 . (fan output level 1). td1fanlevel2 ~ tr2fanlevel2 bit 7 6 5 4 3 2 1 0 name reserved tempfanlevel2 reset 0 10 hex bit description 7-6 reserved. 5-0 tempfanlevel2 . (fan output level 2). td1fanlevel3 ~ tr2fanlevel3 bit 7 6 5 4 3 2 1 0 name reserved tempfanlevel3 reset 0 18 hex bit description 7-6 reserved. 5-0 tempfanlevel3 . (fan output level 3). td1fanlevel4 ~ tr2fanlevel4 bit 7 6 5 4 3 2 1 0 name reserved tempfanlevel4 reset 0 20 hex
W83793G publication release date: dec. 11, 2006 - 81 - revision 1.0 bit description 7-6 reserved. 5-0 tempfanlevel4 . (fan output level 4). td1fanlevel5 ~ tr2fanlevel5 bit 7 6 5 4 3 2 1 0 name reserved tempfanlevel5 reset 0 30 hex bit description 7-6 reserved. 5-0 tempfanlevel5 . (fan output level 5). td1fanlevel6 ~ tr2fanlevel6 bit 7 6 5 4 3 2 1 0 name reserved tempfanlevel6 reset 0 38 hex bit description 7-6 reserved. 5-0 tempfanlevel6 . (fan output level 6). see also: toltemp , fanctrlmode , smart fan ii mode . 8.12 peci control registers intel? new generation cpus such as presler begin to support new single wire digital temperature monitor interface which is called p latform e nvironment c ontrol i nterface or peci. W83793G supports the peci* version 1.0 for these new generation cpus. all peci control registers are allocated in bank 0. pin 1, pclk, is the timing base of peci control ci rcuit, if peci function is desired, pin 1 is required to feed a 48mhz clock.
W83793G - 82 - 8.12.1 peci register map three control registers and 2 status registers are listed here. the detailed operation of peci host can be referred to below figure. mnemonic register name type agtconfig agent configuration register rw agt1tcontrol | agt4tcontrol tcontrol register rw reportstyle peci report temperature style register rw peciwarning peci warning flag register ro agt1reltemph/l | agt4reltemph/l agent relative temperature registers ro
W83793G publication release date: dec. 11, 2006 - 83 - revision 1.0 everytime W83793G peci host detects user enable an agent by setting agten , it start to ping if the client really exist. if not true, it set peciabsent flag to inform host; otherwise it continue to issue gettemp0 or gettemp1 (when dm1exist asserted). a three-level fault queue is made to ensure host can get correct temperature and return. 8.12.2 peci register details 8.12.2.1 agent configuration register (agtconfig) this register commands peci host to proceed related agents and domains, only agent or domain specified in this register will proc eed peci transactions. it is reset as 00 hex . location : agtconfig - bank 0 address d0 hex type : read write reset : vsb5v(pin 7) rising, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set.
W83793G - 84 - agtconfig bit 7 6 5 4 3 2 1 0 name agt4en agt3en agt2en agt1en agt4d1 agt3d1 agt2d1 agt1d1 reset 0 0 0 0 0 0 0 0 bit description 7 agt4en ( agent 4 enable bit). 0 bin : agent 4 is disabled. 1 bin : agent 4 enabled. 6 agt3en ( agent 3 enable bit). 0 bin : agent 3 is disabled. 1 bin : agent 3 enabled. 5 agt2en ( agent 2 enable bit). 0 bin : agent 2 is disabled. 1 bin : agent 2 enabled. 4 agt1en ( agent 1 enable bit). 0 bin : agent 1 is disabled. 1 bin : agent 1 enabled. 3 agt4d1 ( agent 4 domain 1 enable bit). 0 bin : agent 4 does not have domain 1. 1 bin : agent 4 have domain 1. 2 agt3d1 ( agent 3 domain 1 enable bit). 0 bin : agent 3 does not have domain 1. 1 bin : agent 3 have domain 1. 1 agt2d1 ( agent 2 domain 1 enable bit). 0 bin : agent 2 does not have domain 1. 1 bin : agent 2 have domain 1. 0 agt1d1 ( agent 1 domain 1 enable bit). 0 bin : agent 1 does not have domain 1. 1 bin : agent 1 have domain 1. 8.12.2.2 agent tcontrol register (agttcontrol) intel? cpu introduces a tcontrol concept on te mperature management. in presler generation cpus, tcontrol can be read from cpu regist er by bios and refill to W83793G registers. our default setup is 70 , which is 10 higher than templevel67 . in later generation cpus, cpu might only response the tcontrol value as an offset temperature to prochot# assertion. it is reset as 46 hex .
W83793G publication release date: dec. 11, 2006 - 85 - revision 1.0 location : agt1tcontrol - bank 0 address d1 hex agt2tcontrol - bank 0 address d2 hex agt3tcontrol - bank 0 address d3 hex agt4tcontrol - bank 0 address d4 hex type : read / write reset : vsb5v(pin 7) rising, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set. agt1tcontrol~agt4tcontrol bit 7 6 5 4 3 2 1 0 name reserved tcontrol temperature reset 0 1 0 0 0 1 1 0 bit description 7 reserved. 6-0 tcontrol ( tcontrol temperature setting). tcontrol must always be a positive va lue, negative value will introduce abnormal temperature response. 8.12.2.3 peci report temperature style register (reportstyle) reportstyle controls which value being loaded into absolute temp or relative temp. if rthigh, peci host will automatically compares the highest temperature domain and load it into abs/rel-temp. if rthigh = 0, rtdm will return domain 0 temperature if set 0, return domain 1 temperature if set 1. it is reset as 00 hex . location : reportstyle - bank 0 address d5 hex type : read / write reset : vsb5v(pin 7) rising, vdd5v(pin 25) rising @ rst_vdd_md(cr40.bit4) set. reportstyle bit 7 6 5 4 3 2 1 0 name reserved rthigh rtd4 rtd3 rtd2 rtd1 reset 0 0 0 0 0 0 0 0
W83793G - 86 - bit description 7-5 reserved. 4 rthigh (return high temperature). 0 bin : return domain by rtd selection (rtd1~rtd4). 1 bin : return highest temperature in the same agent. 3 rtd4 (agent 4 return domain 1 enable bit). on ly take effect when rthigh deasserts. 0 bin : agent 4 always return domain 0. 1 bin : agent 4 always return domain 1. 2 rtd3 (agent 3 return domain 1 enable bit). on ly take effect when rthigh deasserts. 0 bin : agent 3 always return domain 0. 1 bin : agent 3 always return domain 1. 1 rtd2 (agent 2 return domain 1 enable bit). on ly take effect when rthigh deasserts. 0 bin : agent 2 always return domain 0. 1 bin : agent 2 always return domain 1. 0 rtd1 (agent 1 return domain 1 enable bit). on ly take effect when rthigh deasserts. 0 bin : agent 1 always return domain 0. 1 bin : agent 1 always return domain 1. 8.12.2.4 peci warning flag register (peciwarning) few warnings may be generated while peci protocol applies. first, peci host may not able to detect a peci client (or say, client does not reponse to host ping() command), in this case peci issue a flag called absent to inform users it cannot detect the c lient. another case is about the peci client return bad fcs in successive 3 time polling, host w ill issue an alert flag. it is reset as 00 hex . location: peciwarning - bank 0 address d6 hex type: read only reset: vsb5v (pin 7) rising, vdd5v (pin 25) rising @ rst_vdd_md (cr40.bit4) set. peciwarning bit 7 6 5 4 3 2 1 0 name absent4 absent3 absent2 absent1 alert4 alert3 alert2 alert1 reset 0 0 0 0 0 0 0 0
W83793G publication release date: dec. 11, 2006 - 87 - revision 1.0 bit description 7 absent4 (peci agent 4 absent bit). 0 bin : agent 4 is detected. 1 bin : agent 4 cannot be detected. 6 absent3 (peci agent 3 absent bit). 0 bin : agent 3 is detected. 1 bin : agent 3 cannot be detected. 5 absent2 (peci agent 2 absent bit). 0 bin : agent 2 is detected. 1 bin : agent 2 cannot be detected. 4 absent1 (peci agent 1 absent bit). 0 bin : agent 1 is detected. 1 bin : agent 1 cannot be detected. 3 alert4 (peci agent 4 alert bit). 0 bin : agent 4 has good fcs. 1 bin : agent 4 has bad fcs in last 3 transactions. 2 alert3 (peci agent 3 alert bit). 0 bin : agent 3 has good fcs. 1 bin : agent 3 has bad fcs in last 3 transactions. 1 alert2 (peci agent 2 alert bit). 0 bin : agent 2 has good fcs. 1 bin : agent 2 has bad fcs in last 3 transactions. 0 alert1 (peci agent 1 alert bit). 0 bin : agent 1 has good fcs. 1 bin : agent 1 has bad fcs in last 3 transactions. while peci is activated, alert flag will be asserted when corresponding agent return successive 3 time bad fcs. in this case, W83793G will think this agent has some problem in interface, and for safty reason W83793G will turn on the related fan to full speed in smartfan mode. the fan and peci agent relationship is defined in tempfanselect registers. 8.12.2.5 agent relative temperature register (agtreltemp) these registers return the raw data retrieved from peci interface. they may be the error code (range: 8000h~81ffh) or relative temperature to proc essor defined prochot#. error code will only update in agtreltemp , absolute temp will not be updated when error code received. if returnhigh mechanism is activated, normal temperature will al ways return first. in case both 2 domain returns error, return priority will be overflow error > u nderflow error > missing diode > general error. reset value is 8001 hex due to peci is default turned off, in peci, 8001 hex means diode missing.
W83793G - 88 - location: agt1reltemph - bank 0 address d8 hex agt1reltempl - bank 0 address d9 hex agt2reltemph - bank 0 address da hex agt2reltempl - bank 0 address db hex agt3reltemph - bank 0 address dc hex agt3reltempl - bank 0 address dd hex agt4reltemph - bank 0 address de hex agt4reltempl - bank 0 address df hex type: read only reset: vsb5v (pin 7) rising, vdd5v (pin 25) rising @ rst_vdd_md (cr40.bit4) set. agt1reltemph/l~agt4reltemph/l bit 7 6 5 4 3 2 1 0 name sign temperature[8:2] reset 1 0 0 0 0 0 0 0 name temperature[1:0] temp_2 temp_4 temp_8 temp_16 temp_32 temp_64 reset 0 0 0 0 0 0 0 1 bit description 15 sign bit . in peci protocol, this bit should always be 1 to represent a negative temperature. 14-6 temperature the integer part of relative temperature. 5 temp_2 . 0.5 unit. 4 temp_4 . 0.25 unit. 3 temp_8 . 0.125 unit. 2 temp_16 . 0.0625 unit. 1 temp_32 . 0.03125 unit. 0 temp_64 . 0.015625 unit. in some occasion, the peci interface will return the abnormal states of the peci bus other than temperature, all these information will be recorded in agtreltemp , and in some cases W83793G will also do further processing for alert mechanism. t he following describes these code and their effects to W83793G.
W83793G publication release date: dec. 11, 2006 - 89 - revision 1.0 error code description W83793G host operation 8000 hex general sensor error 8001 hex sensing device missing no further processing. 8002 hex operational, but temperature is lower than sensor operation range. force writing back temperature with 0 in temperature readouts.(bank 0 index 1c hex ~ 1f hex ) 8003 hex operational, but temperature is higher than sensor operation range. force writing back temperature with 127 in temperature readouts.(bank 0 index 1c hex ~ 1f hex ) 8004 hex 81ff hex reserved. no further operation. besides error conditions or bad fcs, normal temperature will be wrote back to temperature readouts with the sum of agtreltemp and tcontrol . 8.13 asf control registers asf or a lert s tandard f ormat provides remote system abilit ies to monitor, discover and manage the local platform. all asf control registers are allocated in bank 1*. *about the bank selection, please reference bank select register located at address 00 hex. 8.13.1 asf register map 8.13.1.1 smbus arp udid control registers
W83793G - 90 - before activating asf, user must go through the ar p (address resolution protocol) to dynamically get a valid address to manipulate asf commands. in arp, a very important id must be defined to distinguish different devices, called udid (u nique d evice id entifier). registers in this section are used to setup the udid content. for detailed operation of arp and udid, you can refer to smbus specification version 2.0 ( http://www.smbus.org/specs/smbus20.pdf ) section 5.6 page 34. 8.13.1.2 asf sensor entity definition registers in asf sensor, each sensor channel has 2 parameters to tell asf host its related location information on the platform. they are entity instance and entity id. in case of user uses the temperature sensor in locations different with default specified, W83793G provides all channel parameter programmable to fit customers? application. mnemonic register name type udiddevcap. udid device capability register ro udidversion. udid version number register ro udidvendorh. udidvendorl. udid vendor id high/low byte register ro udiddevh. udiddevl. udid device id high/low byte register rw udidifh. udidifl. udid interface high/low byte register rw udidsubvenh. udidsubvenl. udid subsystem vendor id high/low byte registers rw udidsubdevh. udidsubdevl. udid subsystem device id high/low byte registers rw udidspeid1. udidspeid4. udid vendor specific id byte 1~4 rw rng1. rng4. random number generator byte 1~4 ro asfaddr. asf assigned address register ro
W83793G publication release date: dec. 11, 2006 - 91 - revision 1.0 for details of entity id, you can refer to platform event trap format specification version 1.0 table 6 page 13. mnemonic register name type vca_enty. vcorea enti ty id register rw vcb_enty. vcoreb enti ty id register rw vtt_enty. vtt entity id register rw vdd_enty. vdd entity id register rw vsb_enty. vsb entity id register rw vbat_enty. vbat entity id register rw vsen1_enty. 12vsen_enty. vsen1~12vsen entity id register rw fan1_enty. fan12_enty. fan1~fan12 entity id register rw td1_enty. tr2_enty. td1~tr2 entity id register rw chs_enty. chassis entity register rw
W83793G - 92 - entity instance is a sequential number which help ident ifies this sensor?s location. customer can set the sequence at any order they want. mnemonic register name type entins1. vcorea/vcoreb enti ty instance register rw entins2. vdd/vtt entity instance register rw entins3. vbat/vsb entity instance register rw entins4. vin1/vin2 entity instance register rw entins5. vin3/vin4 entity instance register rw entins6. fan1/fan2 entity instance register rw entins7. fan3/fan4 entity instance register rw entins8. fan5/fan6 entity instance register rw entins9. fan7/fan8 entity instance register rw entins10. fan9/fan10 entity instance register rw entins11. fan11/fan12 enti ty instance register rw entins12. td1/td2 entity instance register rw entins13. td3/td4 entity instance register rw entins14. tr1/tr2 entity instance register rw entins15. chassis entity instance register rw
W83793G publication release date: dec. 11, 2006 - 93 - revision 1.0 a summary of the entity and entity instance is at following table. sensor in W83793G event status index event sensor type event number entity id (programmable) entity instance (programmable) vcorea 00h 02h 01h 01h vcoreb 01h 02h 02h 02h vtt 02h 02h 03h 03h (processor) 03h td1 03h 01h (temperature) 04h 01h td2 04h 01h 05h 02h td3 05h 01h 06h 03h td4 06h 01h 07h 04h tr1 07h 01h 08h 05h tr2 08h 01h 09h 06h 5vdd 09h 02h 0ah 01h vsb 0ah 02h 0bh 02h vbat 0bh 02h 0ch 03h vsen1 0ch 02h (voltage) 0dh 04h vsen2 0dh 02h 0eh 05h 3vsen 0eh 02h 0fh 06h 12vsen 0fh 02h 10h 07h fan1 10h 04h (fan) 11h 01h fan2 11h 04h 12h 02h fan3 12h 04h 13h 03h fan4 13h 04h 14h 04h fan5 14h 04h 15h 07h (system board) 05h fan6 15h 04h 16h 06h fan7 16h 04h 17h 07h fan8 17h 04h 18h 08h fan9 18h 04h 19h 09h fan10 19h 04h 1ah 0ah fan11 1ah 04h 1bh 0bh fan12 1bh 04h 1ch 0ch case open / intrusion 1ch 05h(physical security) 1dh 23h(system chassis) 01h channels in light-green indicates them could be dis abled by multi-function pin selection or control registers.
W83793G - 94 - and according to each channel status, they are expressed in the following terms. description status event sensor type event type event offset event severity temperature sensors upper-critical going high 09h upper-critical going low 08h 10h critical upper-non-critical going high 07h upper-non-critical going low 3h assert 06h 08h non-critical lower-non-critical going high 01h lower-non-critical going low 2h deasser t 01h temperature 01h threshold- based 00h 01h monitor voltage sensors generic over voltage problem 3h 02h 10h normal voltage 2h 07h 01h generic under voltage problem 3h 02h voltage 07h generic- severity 02h 10h fan sensors normal fan speed 2h 07h 01h generic fan failure 3h 04h fan 07h 02h 10h caseopen/ case intrusion case intruded 3h 00h 10h case normal 2h 05h physical security 6fh sensor specific 80h 01h 8.13.1.3 asf remote cont rol definition registers asf function in W83793G also supports the remote control. this function enables mis to remotely power on, power down, or reset while he finds the client computer goes into abnormal. remote control function in W83793G enables mis to use side-band of network interface controller to send asf commands with smbus, its format looks like mnemonic register name type pwronoption. power on control option register rw pwroncmd. remote control power on command register rw pwroffcmd. remote control power down command register rw rstcmd. remote control reset command register rw
W83793G publication release date: dec. 11, 2006 - 95 - revision 1.0 1 7 1 1 8 1 8 1 8 1 1 s slave address wr a command a write data a pec ap control device address 0 0 control command 0 control data value 0 crc checksum 0 ?s? represents ?start? cycle of smbus transaction, ?wr? means ?wri te? flag, ?a? means ?acknowledge? from W83793G, and ?p? indicates a ?stop? cycle. a ll letter in shadow means it is a response from W83793G; otherwise it is a host transmitted signal. last row above shows what is each data meaning, where control device address is the address assigned in the arp process, control command is specified in above registers, and control data option is not supported in W83793G, thus with any va lue in this field W83793G will perform the same action. in alert standard format specification v2.0 , there are two sections describe this. they are section 5.4 at page 76, and section 3.2.4.1 at page 33. 8.13.2 asf register details 8.13.2.1 udid device capability register (udiddevcap) smbus specification working group intends to use device capability to distinguish the arbitration priority of generalgetudid() first. thus the very first byte the udid is device capability, because smbus is a msb first serial protocol and client s ent low will win the arbitration. it is set as c1 hex . location: udidversion - bank 1 address 20 hex type: read only reset: no reset. udiddevcap bit 7 6 5 4 3 2 1 0 name address type reserved pec reset 1 1 0 0 0 0 0 1 bit description 7-6 address type. 00 bin : fixed address device. it?s t he highest priority device. 01 bin : dynamic and persistent address device. 10 bin : dynamic and volatile address device. if power-down, the address needs to reassign at next power on. W83793G asf addre ss will lost while vsb5v not exist. 11 bin : random number device.
W83793G - 96 - continued bit description 5-1 reserved. 0 pec suppot. 0: not known support pec(packe t error code) on this device. 1: pec is supported on this device. 8.13.2.2 udid version number register (udidversion) this field defines the version of udid and silicon for W83793G. it is 08 hex . location: udidversion - bank 1 address 21 hex type: read only reset: no reset udidversion bit 7 6 5 4 3 2 1 0 name reserved udid version silicon version fixed 0 0 0 0 1 0 0 0 bit description 7-6 reserved. 5-3 udid version. 000 bin : reserved. 001 bin : udid version 1. 010 bin -111 bin : reserved for future use. 2-0 silicon version. for W83793G silicon version identification use. 000 bin stands for version a/b. 8.13.2.3 udid vendor id high/low by te register (udidvendorh/l) this field defines winbond vendor id. default is 1050 hex. location: udidvendorh - bank 1 address 22 hex udidvendorl - bank 1 address 23 hex type: read only reset: no reset
W83793G publication release date: dec. 11, 2006 - 97 - revision 1.0 udidvendorh bit 7 6 5 4 3 2 1 0 name vendor id high byte fixed 0 0 0 1 0 0 0 0 udidvendorl bit 7 6 5 4 3 2 1 0 name vendor id low byte fixed 0 1 0 1 0 0 0 0 bit description 15-0 winbond vendor id. 8.13.2.4 udid device id high/low byte register (udiddevh/l) this field defines winbond device id. default is 0100 hex. location: udiddevh - bank 1 address 24 hex udiddevl - bank 1 address 25 hex type: read write reset: vsb5v (pin 7) rising, init reset (cr40.bit7) is set. udiddevh bit 7 6 5 4 3 2 1 0 name device id high byte reset 0 0 0 0 0 0 0 1 udiddevl bit 7 6 5 4 3 2 1 0 name device id low byte reset 0 0 0 0 0 0 0 0 bit description 15-0 winbond device id.
W83793G - 98 - 8.13.2.5 udid interface high/low byte register (udidifh/l) this field defines smbus version and supported protocol. it is reset to 0024 hex. location: udidifh - bank 1 address 26 hex udidifl - bank 1 address 27 hex type: read write reset: vsb5v (pin 7) rising, init reset (cr40.bit7) is set. udidifh bit 7 6 5 4 3 2 1 0 name reserved reset 0 0 0 0 0 0 0 0 udidifl bit 7 6 5 4 3 2 1 0 name reserved ipmi asf oem smbus version reset 0 0 1 0 0 1 0 0 bit description 15-7 reserved. 6 ipmi . this device supports additional interface access capability per ipmi specification. 0: not supported. 1: supported. 5 asf . this device supports additional interface access capability per asf specification. 0: not supported. 1: supported. 4 oem . device supports vendor specific access capability per subsystem vendor id and subsystem device id . 0: not supported. 1: supported. 3-0 smbus version 0 hex : smbus 1.0, not arpable. 1 hex : smbus 1.1, not arpable. 4 hex : smbus 2.0.
W83793G publication release date: dec. 11, 2006 - 99 - revision 1.0 8.13.2.6 udid subsystem vendor id high/ low byte register (udidsubvenh/l) this field defines udid supporting for subsystems. if no subsystem is support ed, it must specify 0000 hex . it is reset to 0000 hex. location: udidsubvenh - bank 1 address 28 hex udidsubvenl - bank 1 address 29 hex type: read write reset: vsb5v (pin 7) rising, init reset (cr40.bit7) is set. udidsubvenh bit 7 6 5 4 3 2 1 0 name udid subsystem vendor id high byte reset 0 0 0 0 0 0 0 0 udidsubvenl bit 7 6 5 4 3 2 1 0 name udid subsystem vendor id low byte reset 0 0 0 0 0 0 0 0 bit description 15-0 udid subsystem vendor. 8.13.2.7 udid subsystem device id high/ low byte register (udidsubdevh/l) this field defines udid supporting for subsystems. if no subsystem is support ed, it must specify 0000 hex . it is reset to 0000 hex. location: udidsubdevh - bank 1 address 2a hex udidsubdevl - bank 1 address 2b hex type: read write reset: vsb5v (pin 7) rising, init reset (cr40.bit7) is set. udidsubvenh bit 7 6 5 4 3 2 1 0 name udid subsystem device id high byte reset 0 0 0 0 0 0 0 0
W83793G - 100 - udidsubvenl bit 7 6 5 4 3 2 1 0 name udid subsystem device id low byte reset 0 0 0 0 0 0 0 0 bit description 15-0 udid subsystem device id. 8.13.2.8 udid vendor-specific id register (udidspecid1/2/3/4) this field defines unique vendor-specific id for eac h W83793G. with this field different W83793G will identified on the same smbus interface, and it is loaded with random number while reset signal received. location : udidspecid1 - bank 1 address 2c hex udidspecid2 - bank 1 address 2d hex udidspecid3 - bank 1 address 2e hex udidspecid4 - bank 1 address 2f hex type: read write reset: vsb5v (pin 7) rising, init reset (cr40.bit7) is set, arp resetdevice command. udidspecid1~udidspecid4 bit 7 6 5 4 3 2 1 0 name udid specific vendor id reset 0 0 0 0 0 0 0 0 bit description 31-0 udid vendor-specific id. 8.13.2.9 random number genera tor register (rng1/2/3/4) W83793G internally generates pseudo random number by using crc generator and internal clock. due to internal clock always having little different deviations, different ic and different power-on time will affect the result of random number. it is reset to ffff hex. location: rng4 - bank 1 address 30 hex rng3 - bank 1 address 31 hex rng2 - bank 1 address 32 hex rng1 - bank 1 address 33 hex
W83793G publication release date: dec. 11, 2006 - 101 - revision 1.0 type: read only reset: none. rng1~rng4 bit 7 6 5 4 3 2 1 0 name random number code reset 0 0 0 0 0 0 0 0 bit description 31-0 random number code. 8.13.2.10 asf assigned address register (asfaddr) after arp host get related device udid, it will st art to assign each device for later usage. W83793G will record this assigned address and set it as defaul t address for asf transacti ons. it is reset to 00 hex. location: asfaddr - bank 1 address 4f hex type: read only reset: vsb5v (pin 7) rising, init reset (cr40.bit7) is set, asfaddr bit 7 6 5 4 3 2 1 0 name asf address reset 0 0 0 0 0 0 0 0 bit description 31-0 asf address . this register will be assigned while arp assignaddress command issued. 8.13.2.11 asf entity/instance registers (enitiy/entins) W83793G supports various channels which can be r eported to host through asf protocol. each sensor channel is associated with an entity (or said location on motherboard) and entity instance. table provides an overall look for these registers. location: vca_enty - bank 1 address 50 hex vcb_enty - bank 1 address 51 hex vtt_enty - bank 1 address 52 hex vdd_enty - bank 1 address 53 hex
W83793G - 102 - vsb_enty - bank 1 address 54 hex vbat_enty - bank 1 address 55 hex vsen1_enty - bank 1 address 56 hex vsen2_enty - bank 1 address 57 hex 3vsen_enty - bank 1 address 58 hex 12vsen_enty - bank 1 address 59 hex fan1_enty - bank 1 address 5a hex fan2_enty - bank 1 address 5b hex fan3_enty - bank 1 address 5c hex fan4_enty - bank 1 address 5d hex fan5_enty - bank 1 address 5e hex fan6_enty - bank 1 address 5f hex fan7_enty - bank 1 address 60 hex fan8_enty - bank 1 address 61 hex fan9_enty - bank 1 address 62 hex fan10_enty - bank 1 address 63 hex fan11_enty - bank 1 address 64 hex fan12_enty - bank 1 address 65 hex td1_enty - bank 1 address 66 hex td2_enty - bank 1 address 67 hex td3_enty - bank 1 address 68 hex td4_enty - bank 1 address 69 hex tr1_enty - bank 1 address 6a hex tr2_enty - bank 1 address 6b hex chs_enty - bank 1 address 6c hex entins1 - bank 1 address 70 hex entins2 - bank 1 address 71 hex entins3 - bank 1 address 72 hex entins4 - bank 1 address 73 hex entins5 - bank 1 address 74 hex entins6 - bank 1 address 75 hex entins7 - bank 1 address 76 hex entins8 - bank 1 address 77 hex entins9 - bank 1 address 78 hex entins10 - bank 1 address 79 hex entins11 - bank 1 address 7a hex
W83793G publication release date: dec. 11, 2006 - 103 - revision 1.0 entins12 - bank 1 address 7b hex entins13 - bank 1 address 7c hex entins14 - bank 1 address 7d hex entins15 - bank 1 address 7e hex type: read / write reset: 5vsb (pin 7) rising. vca_entity bit 7 6 5 4 3 2 1 0 name vcore a entity id. reset 03 hex vcb_entity bit 7 6 5 4 3 2 1 0 name vcore b entity id. reset 03 hex vtt_entity bit 7 6 5 4 3 2 1 0 name vtt entity id. reset 03 hex vdd_entity bit 7 6 5 4 3 2 1 0 name vdd entity id. reset 07 hex vsb_entity bit 7 6 5 4 3 2 1 0 name vsb entity id. reset 07 hex vbat_entity bit 7 6 5 4 3 2 1 0 name vbat entity id. reset 07 hex
W83793G - 104 - vsen1_entity bit 7 6 5 4 3 2 1 0 name vsen1 entity id. reset 07 hex vsen2_entity bit 7 6 5 4 3 2 1 0 name vsen2 entity id. reset 07 hex 3vsen_entity bit 7 6 5 4 3 2 1 0 name 3vsen entity id. reset 07 hex 12vsen_entity bit 7 6 5 4 3 2 1 0 name 12vsen entity id. reset 07 hex fan1_entity bit 7 6 5 4 3 2 1 0 name fan1 entity id. reset 07 hex fan2_entity bit 7 6 5 4 3 2 1 0 name fan2 entity id. reset 07 hex fan3_entity bit 7 6 5 4 3 2 1 0 name fan3 entity id. reset 07 hex
W83793G publication release date: dec. 11, 2006 - 105 - revision 1.0 fan4_entity bit 7 6 5 4 3 2 1 0 name fan4 entity id. reset 07 hex fan5_entity bit 7 6 5 4 3 2 1 0 name fan5 entity id. reset 07 hex fan6_entity bit 7 6 5 4 3 2 1 0 name fan6 entity id. reset 07 hex fan7_entity bit 7 6 5 4 3 2 1 0 name fan7 entity id. reset 07 hex fan8_entity bit 7 6 5 4 3 2 1 0 name fan8 entity id. reset 07 hex fan9_entity bit 7 6 5 4 3 2 1 0 name fan9 entity id. reset 07 hex fan10_entity bit 7 6 5 4 3 2 1 0 name fan10 entity id. reset 07 hex
W83793G - 106 - fan11_entity bit 7 6 5 4 3 2 1 0 name fan11 entity id. reset 07 hex fan12_entity bit 7 6 5 4 3 2 1 0 name fan12 entity id. reset 07 hex td1_entity bit 7 6 5 4 3 2 1 0 name td1 entity id. reset 07 hex td2_entity bit 7 6 5 4 3 2 1 0 name td2 entity id. reset 07 hex td3_entity bit 7 6 5 4 3 2 1 0 name td3 entity id. reset 07 hex td4_entity bit 7 6 5 4 3 2 1 0 name td4 entity id. reset 07 hex tr1_entity bit 7 6 5 4 3 2 1 0 name tr1 entity id. reset 07 hex
W83793G publication release date: dec. 11, 2006 - 107 - revision 1.0 tr2_entity bit 7 6 5 4 3 2 1 0 name tr2 entity id. reset 07 hex chs_entity bit 7 6 5 4 3 2 1 0 name chassis entity id. reset 23 hex entins1 bit 7 6 5 4 3 2 1 0 name vcoreb entity instance vcorea entity instance reset 02 hex 01 hex entins2 bit 7 6 5 4 3 2 1 0 name vdd entity instance vtt entity instance reset 01 hex 03 hex entins3 bit 7 6 5 4 3 2 1 0 name vbat entity instance vsb entity instance reset 03 hex 02 hex entins4 bit 7 6 5 4 3 2 1 0 name vsen2 entity instance vsen1 entity instance reset 05 hex 04 hex entins5 bit 7 6 5 4 3 2 1 0 name 12vsen entity instance 3vsen entity instance reset 07 hex 06 hex
W83793G - 108 - entins6 bit 7 6 5 4 3 2 1 0 name fan2 entity instance fan1 entity instance reset 02 hex 01 hex entins7 bit 7 6 5 4 3 2 1 0 name fan4 entity instance fan3 entity instance reset 04 hex 03 hex entins8 bit 7 6 5 4 3 2 1 0 name fan6 entity instance fan5 entity instance reset 06 hex 05 hex entins9 bit 7 6 5 4 3 2 1 0 name fan8 entity instance fan7 entity instance reset 08 hex 07 hex entins10 bit 7 6 5 4 3 2 1 0 name fan10 entity instance fan9 entity instance reset 0a hex 09 hex entins11 bit 7 6 5 4 3 2 1 0 name fan12 entity instance fan11 entity instance reset 0c hex 0b hex entins12 bit 7 6 5 4 3 2 1 0 name td2 entity instance td1 entity instance reset 02 hex 01 hex
W83793G publication release date: dec. 11, 2006 - 109 - revision 1.0 entins13 bit 7 6 5 4 3 2 1 0 name td4 entity instance td3 entity instance reset 04 hex 03 hex entins14 bit 7 6 5 4 3 2 1 0 name tr2 entity instance tr1 entity instance reset 06 hex 05 hex entins15 bit 7 6 5 4 3 2 1 0 name reserved chassis entity instance reset 00 hex 01 hex bit description 7-0 entity . entity of each sensor channel. 03 hex : processor 07 hex : system board. 23 hex : chassis back panel board. for other entity types, please refer to pet spec. page 13. 8.13.2.12 power on control option register (pwronoption) W83793G supports 2 kinds of power on. one is power on only one time, no matter vdd5v rised or not. the other is W83793G always issues power on cy cles until it detects vdd is already power on. location: pwronoption - bank 1 address 7f hex type: read write reset: vsb5v (pin 7) rising. pwronoption bit 7 6 5 4 3 2 1 0 name winbond test modes pwr1t reset 0 0 0 0 0 0 0 0
W83793G - 110 - bit description 7-1 winbond test mode . test modes for production. winbond strongly suggest customer do not use these registers in case of causing system malfunction. 0 pwr1t (power on one time). 0: always issue power on cycles (pwrbtn_n assert 0.1sec every 1sec) until vdd power on. 1: only issue 1 time power on cycle. 8.13.2.13 power on command register (pwroncmd) asf remote control command supports remote po wer on features, here defines the power on commands accepted by W83793G. location: pwroncmd - bank 1 address 80 hex type: read write reset: vsb5v (pin 7) rising. pwroncmd bit 7 6 5 4 3 2 1 0 name remote power on command reset 11 hex bit description 7-0 remote power on command. 8.13.2.14 power down command register (pwroffcmd) asf remote control command supports remote powe r down features, here defines the power off commands accepted by W83793G. location: pwroffcmd - bank 1 address 81 hex type: read write reset: vsb5v (pin 7) rising. pwroffcmd bit 7 6 5 4 3 2 1 0 name remote power off command reset 12 hex
W83793G publication release date: dec. 11, 2006 - 111 - revision 1.0 bit description 7-0 remote power off command. 8.13.2.15 reset command register (rst cmd) asf remote control command supports remote re set features, here defines the reset commands accepted by W83793G. location: rstcmd - bank 1 address 82 hex type: read write reset: vsb5v (pin 7) rising. rstcmd bit 7 6 5 4 3 2 1 0 name remote reset command reset 10 hex bit description 7-0 remote reset command.
W83793G - 112 - 9. electrical characteristics 9.1 absolute maximum ratings parameter rating unit power supply voltage -0.5 to 7.0 v input voltage -0.5 to vdd+0.5 v operating temperature 0 to +70 c storage temperature -55 to +150 c 9.2 dc characteristics (ta = 0 c to 70 c, 5vdd = 5v 10%, 5vsb =5v 5%, v ss = 0v) parameter sym. min. typ. max. unit conditions out/od 12 ? output buffer or open-drain output pi n with source-sink capability of 12 ma output low voltage v ol 0.4 v i ol = 12 ma output high voltage v oh 2.4 v i oh = -12 ma, ob mode in/odb 12v1sb - bi-directional pin with sink capabilit y of 12 ma and schmitt-trigger level input input low voltage v il 0.4 v 5vdd = 5 v input high voltage v ih 0.6 v 5vdd = 5 v hysteresis v th 0.2 v 5vdd = 5 v output low voltage v ol 0.4 v i ol = 12 ma input high leakage i lih +10 a v in = vdd input low leakage i lil -10 a v in = 0v in/odb 12tsb - ttl level bi-directional pin with sink capability of 12 ma and schmitt-trigger level input input low voltage v il 0.8 v 5vdd = 5 v input high voltage v ih 2.0 v 5vdd = 5 v hysteresis v th 1.2 v 5vdd = 5 v output low voltage v ol 0.4 v i ol = 12 ma input high leakage i lih +10 a v in = vdd input low leakage i lil -10 a v in = 0v outb 12b - ttl level output pin with source-sink capability of 12 ma output low voltage v ol 0.4 v i ol = 12 ma output high voltage v oh 2.4 v i oh = -12 ma
W83793G publication release date: dec. 11, 2006 - 113 - revision 1.0 dc characteristics, continued. parameter sym. min. typ. max. unit conditions odb 12b - open-drain output pin with sink capability of 12 ma output low voltage v ol 0.4 v i ol = 12 ma aout ? analog output n.a. inb v1sb - vid input pin for intel tm vrm10.0, and vrm11 design input low voltage v il 0.4 v input high voltage v ih 0.6 v in tv2sb - vid input pin for amd tm vrm design input low voltage v il 0.8 v input high voltage v ih 1.4 v in/ob v3b ? bi-direction pin with source capabilit y of 6 ma and sink capability of 1 ma for intel tm peci input low voltage v il 0.275v tt 0.5v tt v input high voltage v ih 0.55v tt 0.725v tt v output low voltage v ol 0.25v tt v output high voltage v oh 0.75v tt v hysterisis v hys 0.1v tt v inb tsb - ttl level schmitt-triggered input pin input low voltage v il 0.8 v 5vdd = 5 v input high voltage v ih 2.0 v 5vdd = 5 v hysteresis v th 1.2 v 5vdd = 5 v input high leakage i lih +10 a v in = vdd input low leakage i lil -10 a v in = 0 v
W83793G - 114 - 9.3 ac characteristics 9.3.1 access interface valid data scl sda in sda out t hd;sda t scl t su;dat t su;sto serial bus timing diagram t r t r t hd;dat parameter symbol min. max. unit scl clock period t - scl 10 us start condition hold time t hd;sda 4.7 us stop condition setup-up time t su;sto 4.7 us data to scl setup time t su;dat 150 ns data to scl hold time t hd;dat 270 ns scl and sda rise time t r 1.0 us scl and sda fall time t f 300 ns
W83793G publication release date: dec. 11, 2006 - 115 - revision 1.0 9.3.2 dynamic vcore limit setting if dynamic vid function enable, vcore channel high/low limit will change in accordance with vid table. when vidin value change, internal vidchg signal will set until vidin value has stabled more than 1ms. new vcore high/low limit will set at falling edge of vidchg and vcore channel will enable monitor at the same time. vidin vidchg vcore high/low limit vcore disable monitor ~1ms
W83793G - 116 - 9.3.3 power on reset the power-on reset threshold is 4.3v (typical). w hen vcc crosses this threshold, the internal reset signal will be asserted for 3us. during this time per iod, W83793G is in the reset state. when the internal reset signal is de-asserted, W83793G is in the operating state. in the operating state, if vcc dr ops below 4.0v and then rises above 4. 3v, the internal reset signal will be asserted immediately. fig 1 illustrates the reset mechanism. figure 1. 10. order information part no. package remarks W83793G ssop56 pb-free package 0v 4.0v 4.3v 5v vsb internal reset signal 3us 3us 4.3v 5.0v
W83793G publication release date: dec. 11, 2006 - 117 - revision 1.0 11. appendix 11.1 register summary bank 0 index register name index register name bank 0 address 00-1f 00 hex bank selection 10 hex vcore a readout 01 hex watch dog lock 11 hex vcore b readout 02 hex watch dog enable 12 hex vtt readout 03 hex watch dog status 13 hex 04 hex watch dog timer 14 hex vsen1 readout 05 hex vida input value 15 hex vsen2 readout 06 hex vidb input value 16 hex 3vsen readout 07 hex vida latch 17 hex 12vsen readout 08 hex vidb latch 18 hex 5vdd readout 09 hex vcore high tolerance 19 hex 5vsb readout 0a hex vcore low tolerance 1a hex vbat readout 0b hex i 2 c address 1b hex vin low bit 0c hex sensor 1/2 address 1c hex td1 readout 0d hex winbond vendor id 1d he x td2 readout 0e hex winbond chip id 1e hex td3 readout 0f hex winbond device id 1f hex td4 readout bank 0 address 20-3f 20 hex tr1 readout 30 hex fan7 count low byte 21 hex tr2 readout 31 hex fan8 count high byte 22 hex temp low bit readout 32 hex fan8 count low byte 23 hex fan1 count high byte 33 hex fan9 count high byte 24 hex fan1 count low byte 34 hex fan9 count low byte 25 hex fan2 count high byte 35 hex fan10 count high byte 26 hex fan2 count low byte 36 hex fan10 count low byte 27 hex fan3 count high byte 37 hex fan11 count high byte 2a hex fan4 count low byte 3a hex fan12 count low byte 2b hex fan5 count high byte 3b hex 2c hex fan5 count low byte 3c hex
W83793G - 118 - register summary, continued. index register name index register name 2d hex fan6 count high byte 3d hex 2e hex fan6 count low byte 3e hex 2f hex fan7 count high byte 3f hex bank 0 address 40-5f 40 hex configuration 50 hex smi/irq control 41 hex interrupt status 1 51 hex ovt control 42 hex interrupt status 2 52 hex ovt/beep global enable 43 hex interrupt status 3 53 hex beep control 1 44 hex interrupt status 4 54 hex beep control 2 45 hex interrupt status 5 55 hex beep control 3 46 hex interrupt mask 1 56 hex beep control 4 47 hex interrupt mask 2 57 hex beep control 5 48 hex interrupt mask 3 58 hex multi-function pin control 49 hex interrupt mask 4 59 hex vid control 4a hex interrupt mask 5 5a hex td1 configuration 4b hex real time status 1 5b hex td2 configuration 4c hex real time status 2 5c hex fanin control 4d hex real time status 3 5d hex fanin redirection 4e hex real time status 4 5e hex td mode select 4f hex real time status 5 5f hex tr mode select bank 0 address 60-7f 60 hex vcorea high limit 70 hex 12vsen high limit 61 hex vcorea low limit 71 hex 12vsen low limit 62 hex vcoreb high limit 72 hex 5vdd high limit 63 hex vcoreb low limit 73 hex 5vdd low limit 64 hex vtt high limit 74 hex 5vsb high limit 65 hex vtt low limit 75 hex 5vsb low limit 66 hex 76 hex vbat high limit 67 hex 77 hex vbat low limit 68 hex high limit low bit 78 hex td1 critical 69 hex low limit low bit 79 hex td1 critical hysterisis 6a hex vsen1 high limit 7a hex td1 warning
W83793G publication release date: dec. 11, 2006 - 119 - revision 1.0 register summary, continued. index register name index register name 6b hex vsen1 low limit 7b hex td1 warning hysterisis 6c hex vsen2 high limit 7c hex td2 critical 6d hex vsen2 low limit 7d hex td2 critical hysterisis 6e hex 3vsen high limit 7e hex td2 warning 6f hex 3vsen low limit 7f hex td2 warning hysterisis bank 0 address 80-9f 80 hex td3 critical 90 hex fan1 limit high byte 81 hex td3 critical hysterisis 91 hex fan1 limit low byte 82 hex td3 warning 92 hex fan2 limit high byte 83 hex td3 warning hysterisis 93 hex fan2 limit low byte 84 hex td4 critical 94 hex fan3 limit high byte 85 hex td4 critical hysterisis 95 hex fan3 limit low byte 86 hex td4 warning 96 hex fan4 limit high byte 87 hex td4 warning hysterisis 97 hex fan4 limit low byte 88 hex tr1 critical 98 he x fan5 limit high byte 89 hex tr1 critical hysterisis 99 hex fan5 limit low byte 8a hex tr1 warning 9a hex fan6 limit high byte 8b hex tr1 warning hysterisis 9b hex fan6 limit low byte 8c hex tr2 critical 9c hex fan7 limit high byte 8d hex tr2 critical hysterisis 9d hex fan7 limit low byte 8e hex tr2 warning 9e hex fan8 limit high byte 8f hex tr2 warning hysterisis 9f hex fan8 limit low byte bank 0 address a0-bf a0 hex fan9 limit high byte b0 hex fan output style 1 a1 hex fan9 limit low byte b1 hex fan output style 2 a2 hex fan10 limit high byte b2 hex fan default speed a3 hex fan10 limit low byte b3 hex fan1 duty a4 hex fan11 limit high byte b4 hex fan2 duty a5 hex fan11 limit low byte b5 hex fan3 duty a6 hex fan12 limit high byte b6 hex fan4 duty a7 hex fan12 limit low byte b7 hex fan5 duty a8 hex td1 temperature offset b8 hex fan6 duty
W83793G - 120 - register summary, continued. index register name index register name a9 hex td2 temperature offset b9 hex fan7 duty aa hex td3 temperature offset ba hex fan8 duty ab hex td4 temperature offset bb hex fan1 output prescalar ac hex tr1 temperature offset bc hex fan2 output prescalar ad hex tr2 temperature offset bd hex fan3 output prescalar ae hex be hex fan4 output prescalar af hex bf hex fan5 output prescalar bank 0 address c0-df c0 hex fan6 output prescalar d5 hex peci return domain c1 hex fan7 output prescalar d6 hex peci warning flags c2 hex fan8 output prescalar d7 hex c3 hex step up time d8 hex peci agent1 reltemph c4 hex step down time d9 hex peci agent1 reltempl c5 hex critical temperature da hex peci agent2 reltemph d0 hex peci agent configure db hex peci agent2 reltempl d1 hex peci agent1 tcontrol dc hex peci agent3 reltemph d2 hex peci agent2 tcontrol dd hex peci agent3 reltempl d3 hex peci agent3 tcontrol de hex peci agent4 reltemph d4 hex peci agent4 tcontrol df hex peci agent4 reltempl bank 1 index register name index register name bank 1 address 00-1f 00 hex bank select 0e hex winbond chip id 0d hex winbond vendor id 0f hex winbond device id bank 1 address 20-33 20 hex udid device capability 2a hex udid subdevice id high 21 hex udid version number 2b hex udid subdevice id low 22 hex udid vendor id high 2c hex udid specific vendor id1 23 hex udid vendor id low 2d hex udid specific vendor id2 24 hex udid device id high 2e hex udid specific vendor id3 25 hex udid device id low 2f hex udid specific vendor id4
W83793G publication release date: dec. 11, 2006 - 121 - revision 1.0 bank 1, continued. index register name index register name 26 hex udid interface high byte 30 hex random number 1 27 hex udid interface low byte 31 hex random number 2 28 hex udid subvendor id high 32 hex random number 3 29 hex udid subvendor id low 33 hex random number 4 bank 1 address 40 40 hex arp assigned address bank 1 address 50-6f 50 hex vcorea entity id 60 hex fan7 entity id 51 hex vcoreb entity id 61 hex fan8 entity id 52 hex vtt entity id 62 hex fan9 entity id 53 hex vdd entity id 63 hex fan10 entity id 54 hex vsb5v entity id 64 hex fan11 entity id 55 hex vbat entity id 65 hex fan12 entity id 56 hex vsen1 entity id 66 hex td1 entity id 57 hex vsen2 entity id 67 hex td2 entity id 58 hex 3vsen entity id 68 hex td3 entity id 59 hex 12vsen entity id 69 hex td4 entity id 5a hex fan1 entity id 6a hex tr1 entity id 5b hex fan2 entity id 6b hex tr2 entity id 5c he x fan3 entity id 6c hex chassis entity id 5d hex fan4 entity id 6d hex 5e hex fan5 entity id 6e hex 5f hex fan6 entity id 6f hex bank 1 address 70-8f 70 hex vcorea/vcoreb entityid 80 hex remote poweron command 71 hex vdd/vtt entityid 81 hex remote power off command 72 hex vbat/vsb entityid 82 hex remote reset command 73 hex vcorea/vcoreb entityid 83 hex 74 hex vsen1/vsen2 entityid 84 hex 75 hex 12vsen/3vsen entityid 85 hex 76 hex fan1/2 entityid 86 hex 77 hex fan3/4 entityid 87 hex
W83793G - 122 - bank 1, continued. index register name index register name 78 hex fan5/6 entityid 88 hex 79 hex fan7/8 entityid 89 hex 7a hex fan9/10 entityid 8a hex 7b hex fan11/12 entityid 8b hex 7c hex td1/2 entityid 8c hex 7d hex td3/4 entityid 8d hex 7e hex chassis entityid 8e hex 7f hex power on option 8f hex bank 2 index register name index register name bank 2 address 00-1f 00 hex bank select 10 hex td1 target temperature 01 hex td1 fan mapping select 11 hex td2 target temperature 02 hex td2 fan mapping select 12 hex td3 target temperature 03 hex td3 fan mapping select 13 hex td4 target temperature 04 hex td4 fan mapping select 14 hex tr1 target temperature 05 hex tr1 fan mapping select 15 hex tr2 target temperature 06 hex tr2 fan mapping select 16 hex 07 hex fan control mode select 17 hex 08 hex td1/2 temp tolerance 18 hex fan1 nonstop duty cycle 09 hex td3/4 temp tolerance 19 hex fan2 nonstop duty cycle 0a hex tr1/2 temp tolerance 1a hex fan3 nonstop duty cycle 0b hex 1b hex fan4 nonstop duty cycle 0c hex 1c hex fan5 nonstop duty cycle 0d hex winbond vendor id 1d hex fan6 nonstop duty cycle 0e hex winbond chip id 1e hex fan7 nonstop duty cycle 0f hex winbond device id 1f hex fan8 nonstop duty cycle bank 2 address 20-3f 20 hex fan1 start duty cycle 30 hex td1 temp level01 21 hex fan2 start duty cycle 31 hex td1 temp level12 22 hex fan3 start duty cycle 32 hex td1 temp level23 23 hex fan4 start duty cycle 33 hex td1 temp level34
W83793G publication release date: dec. 11, 2006 - 123 - revision 1.0 bank 2, continued. index register name index register name 24 hex fan5 start duty cycle 34 hex td1 temp level45 25 hex fan6 start duty cycle 35 hex td1 temp level56 26 hex fan7 start duty cycle 36 hex td1 temp level67 27 hex fan8 start duty cycle 37 hex 28 hex fan1 stop time 38 hex td1 fan level0 29 hex fan2 stop time 39 hex td1 fan level1 2a hex fan3 stop time 3a hex td1 fan level2 2b hex fan4 stop time 3b hex td1 fan level3 2c hex fan5 stop time 3c hex td1 fan level4 2d hex fan6 stop time 3d hex td1 fan level5 2e hex fan7 stop time 3e hex td1 fan level6 2f hex fan8 stop time 3f hex bank 2 address 40-5f 40 hex td2 temp level01 50 hex td3 temp level01 41 hex td2 temp level12 51 hex td3 temp level12 42 hex td2 temp level23 52 hex td3 temp level23 43 hex td2 temp level34 53 hex td3 temp level34 44 hex td2 temp level45 54 hex td3 temp level45 45 hex td2 temp level56 55 hex td3 temp level56 46 hex td2 temp level67 56 hex td3 temp level67 47 hex 57 hex 48 hex td2 fan level0 58 hex td3 fan level0 49 hex td2 fan level1 59 hex td3 fan level1 4a hex td2 fan level2 5a hex td3 fan level2 4b hex td2 fan level3 5b hex td3 fan level3 4c hex td2 fan level4 5c hex td3 fan level4 4d hex td2 fan level5 5d hex td3 fan level5 4e hex td2 fan level6 5e hex td3 fan level6 4f hex 5f hex bank 2 address 60-7f 60 hex td4 temp level01 70 hex tr1 temp level01 61 hex td4 temp level12 71 hex tr1 temp level12
W83793G - 124 - bank 1, continued. index register name index register name 62 hex td4 temp level23 72 hex tr1 temp level23 63 hex td4 temp level34 73 hex tr1 temp level34 64 hex td4 temp level45 74 hex tr1 temp level45 65 hex td4 temp level56 75 hex tr1 temp level56 66 hex td4 temp level67 76 hex tr1 temp level67 67 hex 77 hex 68 hex td4 fan level0 78 hex tr1 fan level0 69 hex td4 fan level1 79 hex tr1 fan level1 6a hex td4 fan level2 7a hex tr1 fan level2 6b hex td4 fan level3 7b hex tr1 fan level3 6c hex td4 fan level4 7c hex tr1 fan level4 6d hex td4 fan level5 7d hex tr1 fan level5 6e hex td4 fan level6 7e hex tr1 fan level6 6f hex 7f hex bank 2 address 80-8f 80 hex tr2 temp level01 88 hex tr2 fan level0 81 hex tr2 temp level12 89 hex tr2 fan level1 82 hex tr2 temp level23 8a hex tr2 fan level2 83 hex tr2 temp level34 8b hex tr2 fan level3 84 hex tr2 temp level45 8c hex tr2 fan level4 85 hex tr2 temp level56 8d hex tr2 fan level5 86 hex tr2 temp level67 8e hex tr2 fan level6 87 hex 8f hex
W83793G publication release date: dec. 11, 2006 - 125 - revision 1.0 12. the top marking left winbond logo. first line ic part number: w83793r ; r means ssop, leaded package. second line serial number third line tracking code: 6 06 g b ub for package information 6 package is made in 2006 06 week: 06 g assembly house id; g means gr eatek; a means ase; o means ose c ic version ub mask version left winbond logo. first line ic part number: W83793G ; g means pb-free package. second line serial number third line tracking code: 6 06 g b ub for package information 6 package is made in 2006 06 week: 06 g assembly house id; g means gr eatek; a means ase; o means ose c ic version ub mask version w83793 g 28201234 606gcub w83793 r 28201234 606gcub
W83793G - 126 - 13. package drawing and dimensions (56-pin ssop 300mil) e e b y seating plane c l c l1 0 0.008 0.400 0.292 7.52 0 7.42 8 7.59 10.31 b e d c 18.2 9 10.16 a1 a2 a 10.41 18.54 18.42 2.79 2.34 8 0.299 0.296 0.092 0.110 0.410 0.720 0.730 0.725 0.406 min. dimension in inch symbol dimension in mm min. nom max. max. nom 0.20 e l l1 y 0.008 0.0135 0.005 0.010 0.024 0.032 0.055 0.003 0.20 0.34 0.13 0.25 0.51 0.76 0.64 0.020 0.030 0.025 0.61 0.81 1.40 0.08 h e 2.57 0.101 .045 .055 .035 .045 he 0.40/0.50 dia top view end view see detail "a" parting line side view d a1 a2 a detail"a" 0.095 0.012 0.016 0.088 0.090 0.010 0.040 2.41 0.30 0.41 2.24 2.29 0.25 1.02
W83793G publication release date: dec. 11, 2006 - 127 - revision 1.0 important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgi cal implantation, atomic energy control instruments, airplane or spaceship instrument s, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in this datasheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c.

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